0c85453ace
Added the libraries to the repository Preliminary changes to fix slow startup when no network cable is connected
271 lines
13 KiB
C
271 lines
13 KiB
C
/**
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* \file
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*
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* \brief API driver for KSZ8051RNL PHY based on driver for DM9161A PHY PHY.
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* Adapted from the mii.h file provided as part of LWIP under the license below:
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* Only designed to work with the KSZ8051RNL PHY, not yet fully tested.
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*
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* Copyright (c) 2012 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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#ifndef RMII_H_INCLUDED
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#define RMII_H_INCLUDED
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/** \addtogroup eth_phy_rmii
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@{*/
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/** \addtogroup rmii_registers PHY registers Addresses
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@{*/
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#define MII_BMCR 0x0 /**< Basic Mode Control Register */
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#define MII_BMSR 0x1 /**< Basic Mode Status Register */
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#define MII_PHYID1 0x2 /**< PHY Identifier Register 1 */
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#define MII_PHYID2 0x3 /**< PHY Identifier Register 2 */
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#define MII_ANAR 0x4 /**< Auto_negotiation Advertisement Register */
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#define MII_ANLPAR 0x5 /**< Auto_negotiation Link Partner Ability Register */
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#define MII_ANER 0x6 /**< Auto-negotiation Expansion Register */
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#define MII_ANNP 0x7 /**< Auto-Negotiation Next Page */
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#define MII_LPNP 0x8 /**< Link Partner Next Page Ability */
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#define MII_AFE 0x11 /**< AFE Control 1*/
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#define MII_RXER 0x15 /**< RXER Counter*/
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#define MII_OMSO 0x16 /**< Operation Mode Strap Override */
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#define MII_OMSS 0x17 /**< Operation Mode Strap Status */
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#define MII_EXPC 0x18 /**< Expanded Control */
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#define MII_INTCS 0x1B /**< Interrupt Control/Status */
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#define MII_LMDCS 0x1D /**< LinkMD Control/Status */
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#define MII_PC1 0x1E /**< PHY Control 1*/
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#define MII_PC2 0x1F /**< PHY Control 2*/
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/** @}*/
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/** \addtogroup phy_bmcr Basic Mode Control Register (BMCR, 0)
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List Bit definitions: \ref MII_BMCR
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@{*/
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#define MII_RESET (1u << 15) /**< 1= Software Reset; 0=Normal Operation */
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#define MII_LOOPBACK (1u << 14) /**< 1=loopback Enabled; 0=Normal Operation */
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#define MII_SPEED_SELECT (1u << 13) /**< 1=100Mbps; 0=10Mbps */
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#define MII_AUTONEG (1u << 12) /**< Auto-negotiation Enable */
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#define MII_POWER_DOWN (1u << 11) /**< 1=Power down 0=Normal operation */
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#define MII_ISOLATE (1u << 10) /**< 1 = Isolate 0 = Normal operation */
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#define MII_RESTART_AUTONEG (1u << 9) /**< 1 = Restart auto-negotiation 0 = Normal operation */
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#define MII_DUPLEX_MODE (1u << 8) /**< 1 = Full duplex operation 0 = Normal operation */
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#define MII_COLLISION_TEST (1u << 7) /**< 1 = Collision test enabled 0 = Normal operation */
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/** Reserved bits: 6 to 0, Read as 0, ignore on write */
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/** @}*/
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/** \addtogroup phy_bmsr Basic Mode Status Register (BMSR, 1)
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List Bit definitions: \ref MII_BMSR
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@{*/
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#define MII_100BASE_T4 (1u << 15) /**< 100BASE-T4 Capable */
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#define MII_100BASE_TX_FD (1u << 14) /**< 100BASE-TX Full Duplex Capable */
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#define MII_100BASE_TX_HD (1u << 13) /**< 100BASE-TX Half Duplex Capable */
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#define MII_10BASE_T_FD (1u << 12) /**< 10BASE-T Full Duplex Capable */
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#define MII_10BASE_T_HD (1u << 11) /**< 10BASE-T Half Duplex Capable */
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/** Reserved bits: 10 to 7, Read as 0, ignore on write */
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#define MII_MF_PREAMB_SUPPR (1u << 6) /**< MII Frame Preamble Suppression */
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#define MII_AUTONEG_COMP (1u << 5) /**< Auto-negotiation is completed */
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#define MII_REMOTE_FAULT (1u << 4) /**< Remote Fault */
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#define MII_AUTONEG_ABILITY (1u << 3) /**< Auto Configuration Ability */
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#define MII_LINK_STATUS (1u << 2) /**< Link Status */
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#define MII_JABBER_DETECT (1u << 1) /**< Jabber Detect */
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#define MII_EXTEND_CAPAB (1u << 0) /**< Extended Capability */
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/** @}*/
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/** \addtogroup phy_id PHY ID Identifier Register (PHYID, 2,3)
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List definitions: \ref MII_PHYID1, \ref MII_PHYID2
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@{*/
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/**<Assigned to the 3rd through 18th bits of the
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Organizationally Unique Identifier (OUI).
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Kendin Communication’s OUI is 0010A1 (hex)*/
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#define MII_OUI1 0x22
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/**<Assigned to the 19th through 24th bits of the
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Organizationally Unique Identifier (OUI).
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Kendin Communication’s OUI is 0010A1 (hex)*/
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#define MII_OUI2 0x5
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#define MII_MODELN 0x15 /**<Six bit manufacturer’s model number*/
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/** @}*/
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/** \addtogroup phy_neg Auto-negotiation (ANAR, 4; ANLPAR, 5; ANER, 6)
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- Auto-negotiation Advertisement Register (ANAR)
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- Auto-negotiation Link Partner Ability Register (ANLPAR)
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- Auto-negotiation Expansion Register (ANER)
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List Bit definitions: \ref MII_ANAR, \ref MII_ANLPAR \ref MII_ANER
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@{*/
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#define MII_NP (1u << 15) /**< Next page Indication */
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#define MII_ACK (1u << 14) /**< Acknowledge from Link Partner ability register (0x5)*/
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#define MII_RF (1u << 13) /**< Remote Fault */
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#define MII_NO_PAUSE 0x0 /**< [00] = No PAUSE*/
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#define MII_A_PAUSE 0x2 /**< [10] = Asymmetric PAUSE*/
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#define MII_S_PAUSE 0x1 /**< [01] = Symmetric PAUSE[11] = Asymmetric & Symmetric PAUSE */
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#define MII_AS_PAUSE 0x3 /**< [11] = Asymmetric & Symmetric PAUSE */
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#define MII_T4 (1u << 9) /**< 100BASE-T4 Support */
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#define MII_TX_FDX (1u << 8) /**< 100BASE-TX Full Duplex Support */
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#define MII_TX_HDX (1u << 7) /**< 100BASE-TX Support */
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#define MII_10_FDX (1u << 6) /**< 10BASE-T Full Duplex Support */
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#define MII_10_HDX (1u << 5) /**< 10BASE-T Support */
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#define MII_PDF (1u << 4) /**< Local Device Parallel Detection Fault */
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#define MII_LP_NP_ABLE (1u << 3) /**< Link Partner Next Page Able */
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#define MII_NP_ABLE (1u << 2) /**< Local Device Next Page Able */
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#define MII_PAGE_RX (1u << 1) /**< New Page Received */
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#define MII_LP_AN_ABLE (1u << 0) /**< Link Partner Auto-negotiation Able */
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/** Selector: 4 to 0, Protocol Selection Bits */
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#define MII_AN_IEEE_802_3 0x1
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/** @}*/
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/** \addtogroup phy_neg_exp Auto-Negotiation Next Page (ANNP, 7, LPNP,8)
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List Bit definitions: \ref MII_ANNP
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List Bit definitions: \ref MII_LPNP
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@{*/
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#define MII_ANMP (1u << 13) /**< Message Page */
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#define MII_ACK2 (1u << 12) /**< Acknowledge2 */
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#define MII_TOGGLE (1u << 11) /**< Toggle */
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#define MII_ANNP_MSG 0x001 /**< 11-bit wide field to encode 2048 messages */
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/** @}*/
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/** \addtogroup phy_neg_exp Auto-Negotiation Next Page (AFE, 11)
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List Bit definitions: \ref MII_AFE
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@{*/
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#define MII_SOME (1u << 5) /**< Slow Oscillator Mode Enable */
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/** @}*/
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/** \addtogroup phy_neg_exp Auto-Negotiation Next Page (RXER, 15)
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List Bit definitions: \ref MII_RXER
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@{*/
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#define MII_RXERC 0x0000 /**< receive error counter for Symbol Error frames */
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/** @}*/
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/** \addtogroup phy_omso Specified Configuration Register (OMSO, 16)
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List Bit definitions: \ref MII_OMSO
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@{*/
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#define MII_BCO (1u << 9) /**< B-CAST_OFF override */
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#define MII_MB2BO (1u << 7) /**< MII B-to-B override */
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#define MII_RB2BO (1u << 6) /**< RMII B-to-B override */
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#define MII_NTO (1u << 5) /**< NAND Tree override*/
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#define MII_RMIIO (1u << 1) /**< RMII override */
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#define MII_MIIO (1u << 0) /**< MII override */
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/** @}*/
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/** \addtogroup phy_omss Specified Configuration and Status Register (OMSS, 17)
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List Bit definitions: \ref MII_OMSS
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@{*/
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#define MII_PHYADD2 (1u << 15) /**< PHYAD[2] strap-in status */
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#define MII_PHYADD1 (1u << 14) /**< PHYAD[1] strap-in status */
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#define MII_PHYADD0 (1u << 13) /**< PHYAD[0] strap-in status */
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#define MII_BCOSS (1u << 9) /**< B-CAST_OFF strap-in status */
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#define MII_MB2BSS (1u << 7) /**< MII B-to-B strap-in status */
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#define MII_RB2BSS (1u << 6) /**< RMII B-to-B strap-in status */
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#define MII_NTSS (1u << 5) /**< NAND Tree strap-in status */
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#define MII_RMIISS (1u << 1) /**< RMII strap-in status */
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#define MII_MIISS (1u << 0) /**< MII strap-in status */
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/** @}*/
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/** \addtogroup phy_expc Expanded Control (EXPC, 18)
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List Bit definitions: \ref MII_EXPC
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@{*/
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#define MII_EDPDD (1u << 11) /**< EDPD Disabled */
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#define MII_100PR (1u << 10) /**< 100Base-TX Preamble Restore */
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#define MII_10PR (1u << 6) /**< 100Base-TX Preamble Restore */
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/** @}*/
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/** \addtogroup phy_intcs Interrupt Control/Status (INTCS, 1B)
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List Bit definitions: \ref MII_INTCS
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@{*/
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#define MII_JIE (1u << 15) /**< Jabber Interrupt Enable*/
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#define MII_REIE (1u << 14) /**< Receive Error Interrupt Enable */
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#define MII_PRIE (1u << 13) /**< Page Received Interrupt Enable */
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#define MII_PDFIE (1u << 12) /**< Parallel Detect Fault Interrupt Enable */
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#define MII_LPAIE (1u << 11) /**< Link Partner Ack Interrupt Enable */
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#define MII_LDIE (1u << 10) /**< Link Down Interrupt Enable */
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#define MII_RFIE (1u << 9) /**< Remote Fault Interrupt Enable */
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#define MII_LUIE (1u << 8) /**< Link Up Interrupt Enable */
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#define MII_JABI (1u << 7) /**< Jabber Interrupt*/
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#define MII_REI (1u << 6) /**< Receive Error Interrupt*/
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#define MII_PRI (1u << 5) /**< Page Received Interrupt*/
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#define MII_PDFI (1u << 4) /**< Parallel Detect Fault Interrupt */
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#define MII_LPAI (1u << 3) /**< Link Partner Ack Interrupt */
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#define MII_LDI (1u << 2) /**< Link Down Interrupt*/
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#define MII_RFI (1u << 1) /**< Remote Fault Interrupt */
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#define MII_LUI (1u << 0) /**< Link Up Interrupt */
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/** @}*/
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/** \addtogroup phy_lmdcs LinkMD Control/Status (LMDCS, 1D)
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List Bit definitions: \ref MII_LMDCS
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@{*/
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#define MII_CDTE (1u << 15) /**< Cable Diagnostic Test Enable*/
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#define MII_CDTR1 (1u << 14) /**< Cable Diagnostic Test Result BIT 1 */
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#define MII_CDTR0 (1u << 14) /**< Cable Diagnostic Test Result BIT 0 */
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#define MII_SCI (1u << 12) /**< Short Cable Indicator */
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#define MII_CFC (1u << 0) /**< Cable Fault Counter */
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/** @}*/
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/** \addtogroup phy_pc PHY Control 1 Register (PC1, 1E)
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List Bit definitions: \ref MII_PC1
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@{*/
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#define MII_ENPFC (1u << 9) /**< Enable Pause(Flow Control)*/
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#define MII_LNKS (1u << 8) /**< Link Status */
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#define MII_POLS (1u << 7) /**< Polarity Status*/
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#define MII_MDIXS (1u << 5) /**< MDI/MDI-X State*/
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#define MII_ENERGYD (1u << 4) /**< Energy Detect */
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#define MII_PHYISO (1u << 3) /**< PHY Isolate */
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#define MII_OMI_10_HD 0x1 /**< [001] = 10Base-T half-duplex*/
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#define MII_OMI_100_HD 0x2 /**< [010] = 100Base-TX half-duplex*/
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#define MII_OMI_10_FD 0x5 /**< [101] = 10Base-T full-duplex*/
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#define MII_OMI_100_FD 0x6 /**< [110] = 100Base-TX full-duplex*/
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/** @}*/
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/** \addtogroup phy_pc PHY Control 2 Register (PC2, 1F)
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List Bit definitions: \ref MII_PC2
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@{*/
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#define MII_HP_MDIX (1u << 15) /**< HP_MDIX*/
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#define MII_MDIX_SELECT (1u << 14) /**< MDI/MDI-X Select */
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#define MII_PSD (1u << 13) /**< Pair Swap Disable */
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#define MII_FORCE_LINK (1u << 11) /**< Force Link */
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#define MII_POWERSAVE (1u << 10) /**< Power Saving */
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#define MII_INT_LEVEL (1u << 9) /**< Interrupt Level*/
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#define MII_ENJAB (1u << 8) /**< Enable Jabber */
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#define MII_RMII_REF_CLK (1u << 7) /**< RMII Reference Clock Select*/
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#define MII_LED1 (1u << 5) /**< LED mode BIT 1*/
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#define MII_LED0 (1u << 4) /**< LED mode BIT 0*/
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#define MII_TXDIS (1u << 3) /**< Disable Transmitter */
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#define MII_RMLB (1u << 2) /**< Remote Loop-back*/
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#define MII_SQET (1u << 1) /**< Enable SQE Test*/
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#define MII_DDS (1u << 0) /**< Disable Data Scrambling*/
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/** @}*/
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/**@}*/
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#endif /* RMII_H_INCLUDED */
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