4a1072a8e7
Merged in chrishamm's changes including OutputBuffer fix, changes to Roland pin numbers, rr_configfile support in web server, and Roland and inkjet pin numbers moved to Pins_duet.h Merged in wrangellboy's http response changes for compatibility with Edge browser Other minor changes
524 lines
13 KiB
C
524 lines
13 KiB
C
/**
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* \file
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*
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* \brief API driver for KSZ8051RNL PHY based on driver for DM9161A PHY PHY.
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* Adapted from the ethernet_phy.c file provided as part of LWIP under the license below:
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* Only designed to work with the KSZ8051RNL PHY, not yet fully tested.
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*
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* Copyright (c) 2012 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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#include "ethernet_phy.h"
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#include "rmii.h"
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/// @cond 0
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/**INDENT-OFF**/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**INDENT-ON**/
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/// @endcond
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/**
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* \defgroup KSZ8051RNL_ethernet_phy_group PHY component (KSZ8051RNL)
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*
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* Driver for the KSZ8051RNL component. This driver provides access to the main
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* features of the PHY.
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*
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* \section dependencies Dependencies
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* This driver depends on the following modules:
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* - \ref emac_group Ethernet Media Access Controller (EMAC) module.
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*
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* @{
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*/
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/* Max PHY number */
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#define ETH_PHY_MAX_ADDR 8
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/* Ethernet PHY operation max retry count */
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#define ETH_PHY_RETRY_MAX 1000000
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/* Ethernet PHY operation timeout */
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#define ETH_PHY_TIMEOUT 10
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//*****************************AB
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/**
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* \brief Read a Register of the PHY.
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*
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* \param p_emac Pointer to the EMAC instance.
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* \param uc_phy_addr PHY address.
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* \param ul_phy_reg PHY Register to be read
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*
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* Return Register contents
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*/
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uint8_t ethernet_phy_read_register(Emac *p_emac, uint8_t uc_phy_addr, uint32_t ul_phy_reg, uint32_t *p_ul_reg_cont)
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{
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emac_enable_management(p_emac, true);
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uint8_t uc_rc = emac_phy_read(p_emac, uc_phy_addr, ul_phy_reg, p_ul_reg_cont);
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if (uc_rc != EMAC_OK) {
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/* Disable PHY management and start the EMAC transfer */
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emac_enable_management(p_emac, false);
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return uc_rc;
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}
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/* Start the EMAC transfers */
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emac_enable_management(p_emac, false);
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return uc_rc;
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}
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//*****************************AB
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#if 0 // this function is unused in the Duet firmware
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/**
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* \brief Find a valid PHY Address ( from addrStart to 31 ).
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*
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* \param p_emac Pointer to the EMAC instance.
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* \param uc_phy_addr PHY address.
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* \param uc_start_addr Start address of the PHY to be searched.
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*
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* \return 0xFF when no valid PHY address is found.
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*/
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static uint8_t ethernet_phy_find_valid(Emac *p_emac, uint8_t uc_phy_addr,
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uint8_t addrStart)
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{
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uint32_t ul_value = 0;
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uint8_t uc_rc;
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uint8_t uc_cnt;
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uint8_t uc_phy_address = uc_phy_addr;
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emac_enable_management(p_emac, true);
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/* Check the current PHY address */
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uc_rc = uc_phy_address;
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if (emac_phy_read(p_emac, uc_phy_addr, MII_PHYID1, &ul_value) != EMAC_OK) {
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}
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/* Find another one */
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if (ul_value != MII_OUI1) {
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uc_rc = 0xFF;
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for (uc_cnt = addrStart; uc_cnt <= ETH_PHY_MAX_ADDR; uc_cnt++) {
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uc_phy_address = (uc_phy_address + 1) & 0x1F;
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emac_phy_read(p_emac, uc_phy_address, MII_PHYID1, &ul_value);
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if (ul_value == MII_OUI1) {
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uc_rc = uc_phy_address;
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break;
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}
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}
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}
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emac_enable_management(p_emac, false);
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if (uc_rc != 0xFF) {
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emac_phy_read(p_emac, uc_phy_address, MII_OMSS, &ul_value);
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}
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return uc_rc;
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}
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#endif
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/**
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* \brief Perform a HW initialization to the PHY ( via RSTC ) and set up clocks.
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*
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* This should be called only once to initialize the PHY pre-settings.
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* The PHY address is the reset status of CRS, RXD[3:0] (the emacPins' pullups).
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* The COL pin is used to select MII mode on reset (pulled up for Reduced MII).
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* The RXDV pin is used to select test mode on reset (pulled up for test mode).
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* The above pins should be predefined for corresponding settings in resetPins.
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* The EMAC peripheral pins are configured after the reset is done.
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*
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* \param p_emac Pointer to the EMAC instance.
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* \param uc_phy_addr PHY address.
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* \param ul_mck EMAC MCK.
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*
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* Return EMAC_OK if successfully, EMAC_TIMEOUT if timeout.
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*/
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uint8_t ethernet_phy_init(Emac *p_emac, uint8_t uc_phy_addr, uint32_t mck)
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{
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uint8_t uc_rc = EMAC_TIMEOUT;
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/* Configure EMAC runtime clock */
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uc_rc = emac_set_clock(p_emac, mck);
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if (uc_rc != EMAC_OK) {
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return uc_rc;
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}
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/* Check PHY Address - Not used as we know the PHY address*/
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/*
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uint8_t uc_phy = ethernet_phy_find_valid(p_emac, uc_phy_addr, 0);
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if (uc_phy == 0xFF) {
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return uc_phy;
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}
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if (uc_phy != uc_phy_addr) {
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ethernet_phy_reset(p_emac, uc_phy_addr);
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}
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*/
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return uc_rc;
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}
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/**
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* \brief Get the Link & speed settings, and automatically set up the EMAC with the
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* settings.
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*
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* \param p_emac Pointer to the EMAC instance.
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* \param uc_phy_addr PHY address.
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* \param uc_apply_setting_flag Set to 0 to not apply the PHY configurations, else to apply.
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*
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* Return EMAC_OK if successfully, EMAC_TIMEOUT if timeout.
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*/
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uint8_t ethernet_phy_set_link(Emac *p_emac, uint8_t uc_phy_addr, uint8_t uc_apply_setting_flag)
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{
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emac_enable_management(p_emac, true);
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uint8_t uc_phy_address = uc_phy_addr;
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uint32_t ul_stat1;
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uint8_t uc_rc = emac_phy_read(p_emac, uc_phy_address, MII_BMSR, &ul_stat1);
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if (uc_rc != EMAC_OK) {
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/* Disable PHY management and start the EMAC transfer */
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emac_enable_management(p_emac, false);
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return uc_rc;
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}
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if ((ul_stat1 & MII_LINK_STATUS) == 0) {
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/* Disable PHY management and start the EMAC transfer */
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emac_enable_management(p_emac, false);
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return EMAC_INVALID;
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}
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if (uc_apply_setting_flag == 0) {
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/* Disable PHY management and start the EMAC transfer */
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emac_enable_management(p_emac, false);
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return uc_rc;
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}
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// Re-configure Link speed
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bool uc_speed, uc_fd;
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uint32_t ul_stat2;
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uc_rc = emac_phy_read(p_emac, uc_phy_address, MII_PC1, &ul_stat2);
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if (uc_rc != EMAC_OK) {
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// Disable PHY management and start the EMAC transfer
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emac_enable_management(p_emac, false);
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return uc_rc;
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}
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if ((ul_stat1 & MII_100BASE_TX_FD) && (ul_stat2 & MII_OMI_100_FD)) {
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// Set EMAC for 100BaseTX and Full Duplex
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uc_speed = true;
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uc_fd = true;
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}
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else if ((ul_stat1 & MII_10BASE_T_FD) && (ul_stat2 & MII_OMI_10_FD)) {
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// Set MII for 10BaseT and Full Duplex
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uc_speed = false;
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uc_fd = true;
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}
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else if ((ul_stat1 & MII_100BASE_TX_HD) && (ul_stat2 & MII_OMI_100_HD)) {
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// Set MII for 100BaseTX and Half Duplex
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uc_speed = true;
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uc_fd = false;
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}
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else if ((ul_stat1 & MII_10BASE_T_HD) && (ul_stat2 & MII_OMI_10_HD)) {
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// Set MII for 10BaseT and Half Duplex
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uc_speed = false;
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uc_fd = false;
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}
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else {
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// not clear what the default should be here (DC)
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uc_speed = false;
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uc_fd = false;
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}
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emac_set_speed(p_emac, uc_speed);
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emac_enable_full_duplex(p_emac, uc_fd);
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/* Start the EMAC transfers */
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emac_enable_management(p_emac, false);
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return uc_rc;
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}
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/**
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* \brief Issue an auto negotiation of the PHY.
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*
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* \param p_emac Pointer to the EMAC instance.
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* \param uc_phy_addr PHY address.
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*
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* Return EMAC_OK if successfully, EMAC_TIMEOUT if timeout (in which case we can keep calling this).
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* This has been refactored as a state machine, because we must not spend much time calling this when
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* no network cable is connected, otherwise it slows down printing.
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*/
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uint8_t ethernet_phy_auto_negotiate(Emac *p_emac, uint8_t uc_phy_addr)
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{
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static uint8_t state = 0;
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static uint8_t ul_retry_count;
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static uint32_t ul_value;
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static uint32_t ul_phy_anar;
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switch(state)
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{
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case 0:
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{
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emac_enable_management(p_emac, true);
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/* Set up control register */
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uint8_t uc_rc = emac_phy_read(p_emac, uc_phy_addr, MII_BMCR, &ul_value);
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if (uc_rc != EMAC_OK)
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{
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emac_enable_management(p_emac, false);
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state = 0;
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return uc_rc;
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}
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++state;
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}
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break;
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case 1:
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{
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ul_value &= ~MII_AUTONEG; /* Remove auto-negotiation enable */
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ul_value &= ~(MII_LOOPBACK | MII_POWER_DOWN);
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ul_value |= MII_ISOLATE; /* Electrically isolate PHY */
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uint8_t uc_rc = emac_phy_write(p_emac, uc_phy_addr, MII_BMCR, ul_value);
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if (uc_rc != EMAC_OK)
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{
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emac_enable_management(p_emac, false);
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state = 0;
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return uc_rc;
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}
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++state;
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}
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break;
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case 2:
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{
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/*
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* Set the Auto_negotiation Advertisement Register.
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* MII advertising for Next page.
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* 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3.
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*/
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ul_phy_anar = MII_TX_FDX | MII_TX_HDX | MII_10_FDX | MII_10_HDX | MII_AN_IEEE_802_3;
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uint8_t uc_rc = emac_phy_write(p_emac, uc_phy_addr, MII_ANAR, ul_phy_anar);
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if (uc_rc != EMAC_OK)
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{
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emac_enable_management(p_emac, false);
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state = 0;
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return uc_rc;
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}
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++state;
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}
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break;
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case 3:
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{
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/* Read & modify control register */
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uint8_t uc_rc = emac_phy_read(p_emac, uc_phy_addr, MII_BMCR, &ul_value);
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if (uc_rc != EMAC_OK)
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{
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emac_enable_management(p_emac, false);
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state = 0;
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return uc_rc;
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}
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++state;
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}
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break;
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case 4:
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{
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ul_value |= MII_SPEED_SELECT | MII_AUTONEG | MII_DUPLEX_MODE;
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uint8_t uc_rc = emac_phy_write(p_emac, uc_phy_addr, MII_BMCR, ul_value);
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if (uc_rc != EMAC_OK)
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{
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emac_enable_management(p_emac, false);
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state = 0;
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return uc_rc;
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}
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++state;
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}
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break;
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case 5:
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{
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/* Restart auto negotiation */
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ul_value |= MII_RESTART_AUTONEG;
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ul_value &= ~MII_ISOLATE;
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uint8_t uc_rc = emac_phy_write(p_emac, uc_phy_addr, MII_BMCR, ul_value);
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if (uc_rc != EMAC_OK)
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{
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emac_enable_management(p_emac, false);
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state = 0;
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return uc_rc;
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}
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ul_retry_count = 0;
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++state;
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}
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break;
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case 6:
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{
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/* Check if auto negotiation is completed */
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uint8_t uc_rc = emac_phy_read(p_emac, uc_phy_addr, MII_BMSR, &ul_value);
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if (uc_rc != EMAC_OK)
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{
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emac_enable_management(p_emac, false);
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state = 0;
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return uc_rc;
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}
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/* Done successfully */
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if (!(ul_value & MII_AUTONEG_COMP))
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{
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++ul_retry_count;
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if (ul_retry_count >= 10000) // timeout check
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{
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state = 0; // start again
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}
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return EMAC_TIMEOUT;
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}
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++state;
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}
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break;
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case 7:
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{
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uint32_t ul_phy_analpar;
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/* Get the auto negotiate link partner base page */
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uint8_t uc_rc = emac_phy_read(p_emac, uc_phy_addr, MII_ANLPAR, &ul_phy_analpar);
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if (uc_rc != EMAC_OK)
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{
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emac_enable_management(p_emac, false);
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state = 0;
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return uc_rc;
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}
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// The rest only happens once. so we do it all in one go
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uint8_t uc_fd = false;
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uint8_t uc_speed = false;
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/* Set up the EMAC link speed */
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if ((ul_phy_anar & ul_phy_analpar) & MII_TX_FDX)
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{
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/* Set MII for 100BaseTX and Full Duplex */
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uc_speed = true;
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uc_fd = true;
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}
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else if ((ul_phy_anar & ul_phy_analpar) & MII_10_FDX)
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{
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/* Set MII for 10BaseT and Full Duplex */
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uc_speed = false;
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uc_fd = true;
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}
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else if ((ul_phy_anar & ul_phy_analpar) & MII_TX_HDX)
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{
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/* Set MII for 100BaseTX and half Duplex */
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uc_speed = true;
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uc_fd = false;
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}
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else if ((ul_phy_anar & ul_phy_analpar) & MII_10_HDX)
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{
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/* Set MII for 10BaseT and half Duplex */
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uc_speed = false;
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uc_fd = false;
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}
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emac_set_speed(p_emac, uc_speed);
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emac_enable_full_duplex(p_emac, uc_fd);
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emac_enable_rmii(p_emac, ETH_PHY_MODE);
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emac_enable_transceiver_clock(p_emac, true);
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emac_enable_management(p_emac, false);
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state = 0; // in case we get called again
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return EMAC_OK;
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}
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}
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return EMAC_TIMEOUT; // this just means that we needs to be called again
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}
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/**
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* \brief Issue a SW reset to reset all registers of the PHY.
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*
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* \param p_emac Pointer to the EMAC instance.
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* \param uc_phy_addr PHY address.
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*
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* \Return EMAC_OK if successfully, EMAC_TIMEOUT if timeout.
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*/
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uint8_t ethernet_phy_reset(Emac *p_emac, uint8_t uc_phy_addr)
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{
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uint32_t ul_bmcr = MII_RESET;
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uint8_t uc_phy_address = uc_phy_addr;
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uint32_t ul_timeout = ETH_PHY_TIMEOUT;
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uint8_t uc_rc = EMAC_TIMEOUT;
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emac_enable_management(p_emac, true);
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|
|
ul_bmcr = MII_RESET;
|
|
emac_phy_write(p_emac, uc_phy_address, MII_BMCR, ul_bmcr);
|
|
|
|
do {
|
|
emac_phy_read(p_emac, uc_phy_address, MII_BMCR, &ul_bmcr);
|
|
ul_timeout--;
|
|
} while ((ul_bmcr & MII_RESET) && ul_timeout);
|
|
|
|
emac_enable_management(p_emac, false);
|
|
|
|
if (!ul_timeout) {
|
|
uc_rc = EMAC_OK;
|
|
}
|
|
|
|
return (uc_rc);
|
|
}
|
|
|
|
/// @cond 0
|
|
/**INDENT-OFF**/
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
/**INDENT-ON**/
|
|
/// @endcond
|
|
|
|
/**
|
|
* \}
|
|
*/
|