0c85453ace
Added the libraries to the repository Preliminary changes to fix slow startup when no network cable is connected
484 lines
13 KiB
C
484 lines
13 KiB
C
/**
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* \file
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*
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* \brief DMA Controller (DMAC) driver for SAM.
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*
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* Copyright (c) 2012 - 2013 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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#include "dmac.h"
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/**
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* \brief Initialize DMA controller and disable it.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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*/
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void dmac_init(Dmac *p_dmac)
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{
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dmac_disable(p_dmac);
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}
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/**
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* \brief Set DMA priority mode.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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* \param mode Priority mode.
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*/
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void dmac_set_priority_mode(Dmac *p_dmac, dmac_priority_mode_t mode)
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{
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p_dmac->DMAC_GCFG = (p_dmac->DMAC_GCFG & (~DMAC_GCFG_ARB_CFG)) | mode;
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}
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/**
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* \brief Enable DMA Controller.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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*/
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void dmac_enable(Dmac *p_dmac)
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{
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p_dmac->DMAC_EN = DMAC_EN_ENABLE;
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}
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/**
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* \brief Disable DMA Controller.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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*/
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void dmac_disable(Dmac *p_dmac)
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{
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p_dmac->DMAC_EN &= (~DMAC_EN_ENABLE);
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}
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/**
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* \brief Enable DMA interrupt.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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* \param ul_mask Interrupt to be enabled.
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*/
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void dmac_enable_interrupt(Dmac *p_dmac, uint32_t ul_mask)
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{
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p_dmac->DMAC_EBCIER = ul_mask;
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}
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/**
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* \brief Disable DMA interrupt.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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* \param ul_mask Interrupt to be disabled.
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*/
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void dmac_disable_interrupt(Dmac *p_dmac, uint32_t ul_mask)
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{
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p_dmac->DMAC_EBCIDR = ul_mask;
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}
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/**
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* \brief Get DMAC Interrupt Mask.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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*
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* \return DMAC Interrupt mask.
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*/
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uint32_t dmac_get_interrupt_mask(Dmac *p_dmac)
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{
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return (p_dmac->DMAC_EBCIMR);
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}
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/**
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* \brief Get DMAC transfer status.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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*
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* \return DMAC transfer status.
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*/
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uint32_t dmac_get_status(Dmac *p_dmac)
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{
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return (p_dmac->DMAC_EBCISR);
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}
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/**
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* \brief Enable the relevant channel.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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* \param ul_num Channel number.
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*/
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void dmac_channel_enable(Dmac *p_dmac, uint32_t ul_num)
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{
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p_dmac->DMAC_CHER = DMAC_CHER_ENA0 << ul_num;
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}
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/**
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* \brief Disable the relevant channel.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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* \param ul_num Channel number.
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*/
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void dmac_channel_disable(Dmac *p_dmac, uint32_t ul_num)
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{
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p_dmac->DMAC_CHDR = DMAC_CHDR_DIS0 << ul_num;
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}
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/**
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* \brief Check if the relevant channel is enabled.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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* \param ul_num Channel number.
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*
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* \retval 0: disabled.
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* \retval 1: enabled.
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*/
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uint32_t dmac_channel_is_enable(Dmac *p_dmac, uint32_t ul_num)
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{
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if (p_dmac->DMAC_CHSR & (DMAC_CHSR_ENA0 << ul_num)) {
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return 1;
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} else {
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return 0;
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}
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}
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/**
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* \brief Suspend the specified channel and its current context.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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* \param ul_num Channel number.
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*/
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void dmac_channel_suspend(Dmac *p_dmac, uint32_t ul_num)
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{
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p_dmac->DMAC_CHER = DMAC_CHER_SUSP0 << ul_num;
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}
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/**
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* \brief Resume the specified channel transfer (restoring its context).
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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* \param ul_num Channel number.
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*/
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void dmac_channel_resume(Dmac *p_dmac, uint32_t ul_num)
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{
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p_dmac->DMAC_CHDR = DMAC_CHDR_RES0 << ul_num;
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}
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/**
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* \brief Resume the specified channel from an automatic stall state.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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* \param ul_num Channel number.
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*/
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void dmac_channel_keep(Dmac *p_dmac, uint32_t ul_num)
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{
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p_dmac->DMAC_CHER = DMAC_CHER_KEEP0 << ul_num;
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}
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/**
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* \brief Get DMAC channel handler status.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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*
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* \return DMAC channel handler status register.
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*/
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uint32_t dmac_channel_get_status(Dmac *p_dmac)
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{
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return (p_dmac->DMAC_CHSR);
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}
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/**
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* \brief Set DMAC source address of the DMAC channel.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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* \param ul_num Channel number.
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* \param ul_addr Source address.
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*
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* \note This register must be aligned with the source transfer width.
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*/
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void dmac_channel_set_source_addr(Dmac *p_dmac,
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uint32_t ul_num, uint32_t ul_addr)
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{
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p_dmac->DMAC_CH_NUM[ul_num].DMAC_SADDR = ul_addr;
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}
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/**
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* \brief Set DMAC destination address of the DMAC channel.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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* \param ul_num Channel number.
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* \param ul_addr Destination address.
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*
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* \note This register must be aligned with the source transfer width.
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*/
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void dmac_channel_set_destination_addr(Dmac *p_dmac, uint32_t ul_num,
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uint32_t ul_addr)
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{
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p_dmac->DMAC_CH_NUM[ul_num].DMAC_DADDR = ul_addr;
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}
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/**
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* \brief Set DMAC descriptor address of the DMAC channel.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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* \param ul_num Channel number.
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* \param ul_desc Descriptor address.
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*/
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void dmac_channel_set_descriptor_addr(Dmac *p_dmac,
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uint32_t ul_num, uint32_t ul_desc)
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{
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p_dmac->DMAC_CH_NUM[ul_num].DMAC_DSCR = ul_desc;
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}
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/**
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* \brief Set DMAC control A of the DMAC channel.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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* \param ul_num Channel number.
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* \param ul_ctrlA Configuration of control A register.
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*/
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void dmac_channel_set_ctrlA(Dmac *p_dmac, uint32_t ul_num, uint32_t ul_ctrlA)
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{
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p_dmac->DMAC_CH_NUM[ul_num].DMAC_CTRLA = ul_ctrlA;
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}
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/**
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* \brief Set DMAC control B of the DMAC channel.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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* \param ul_num Channel number.
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* \param ul_ctrlB Configuration of control B register.
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*/
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void dmac_channel_set_ctrlB(Dmac *p_dmac, uint32_t ul_num, uint32_t ul_ctrlB)
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{
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p_dmac->DMAC_CH_NUM[ul_num].DMAC_CTRLB = ul_ctrlB;
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}
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/**
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* \brief Set DMAC configuration register of the DMAC channel.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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* \param ul_num Channel number.
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* \param ul_cfg Configuration of CFG register.
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*/
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void dmac_channel_set_configuration(Dmac *p_dmac, uint32_t ul_num,
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uint32_t ul_cfg)
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{
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p_dmac->DMAC_CH_NUM[ul_num].DMAC_CFG = ul_cfg;
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}
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/**
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* \brief Initialize DMAC channel of single buffer transfer.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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* \param ul_num Channel number.
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* \param p_desc Pointer to a transfer descriptor.
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*/
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void dmac_channel_single_buf_transfer_init(Dmac *p_dmac,
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uint32_t ul_num, dma_transfer_descriptor_t *p_desc)
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{
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/* Clear any pending interrupts */
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p_dmac->DMAC_EBCISR;
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dmac_channel_set_source_addr(p_dmac, ul_num, p_desc->ul_source_addr);
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dmac_channel_set_destination_addr(p_dmac, ul_num,
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p_desc->ul_destination_addr);
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dmac_channel_set_descriptor_addr(p_dmac, ul_num, 0);
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dmac_channel_set_ctrlA(p_dmac, ul_num, p_desc->ul_ctrlA);
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dmac_channel_set_ctrlB(p_dmac, ul_num, p_desc->ul_ctrlB);
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}
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/**
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* \brief Initialize DMAC channel of multiple buffer transfer.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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* \param ul_num Channel number.
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* \param p_desc Pointer to a transfer descriptor.
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*/
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void dmac_channel_multi_buf_transfer_init(Dmac *p_dmac,
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uint32_t ul_num, dma_transfer_descriptor_t *p_desc)
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{
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/* Clear any pending interrupts */
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p_dmac->DMAC_EBCISR;
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dmac_channel_set_descriptor_addr(p_dmac, ul_num, (uint32_t)p_desc);
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dmac_channel_set_ctrlB(p_dmac, ul_num, 0);
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}
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/**
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* \brief Stop DMA transfer of the DMAC channel.
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*
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* \note Under normal operation, the hardware disables a channel on transfer
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* completion by clearing the DMAC_CHSR.ENAx register bit.
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* The recommended way for software to disable a channel without losing data
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* is to use the SUSPx bit in conjunction with the EMPTx bit in the Channel
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* Handler Status Register.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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* \param ul_num Channel number.
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*/
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void dmac_channel_stop_transfer(Dmac *p_dmac, uint32_t ul_num)
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{
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uint32_t status;
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status = dmac_channel_get_status(p_dmac);
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if (!(status & (DMAC_CHSR_ENA0 << ul_num))) {
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/* The channel is already stopped. */
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return;
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} else {
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/* Suspend channel and the channel FIFO receives no new data. */
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dmac_channel_suspend(p_dmac, ul_num);
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/* Check if the channel FIFO is empty. */
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do {
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status = dmac_channel_get_status(p_dmac);
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if (status & (DMAC_CHSR_EMPT0 << ul_num)) {
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break;
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}
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} while (1);
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/* Disable the channel. */
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dmac_channel_disable(p_dmac, ul_num);
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/* Clear suspend flag. */
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dmac_channel_resume(p_dmac, ul_num);
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}
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}
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/**
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* \brief Check if the transfer of the DMAC channel is done.
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* This function is used for polling mode.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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* \param ul_num Channel number.
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*
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* \retval 0 - Transferring.
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* \retval 1 - Transfer is done.
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*/
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uint32_t dmac_channel_is_transfer_done(Dmac *p_dmac, uint32_t ul_num)
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{
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uint32_t status;
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status = dmac_channel_get_status(p_dmac);
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if (status & (DMAC_CHSR_ENA0 << ul_num)) {
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return 0;
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} else {
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return 1;
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}
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}
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/**
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* \brief DMAC software single request.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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* \param ul_num Channel number.
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* \param ul_src_req Request a source transfer.
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* \param ul_dst_req Request a destination transfer.
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*/
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void dmac_soft_single_transfer_request(Dmac *p_dmac,
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uint32_t ul_num, uint32_t ul_src_req, uint32_t ul_dst_req)
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{
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uint32_t req;
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req = ul_src_req ? DMAC_SREQ_SSREQ0 : 0;
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req |= ul_dst_req ? DMAC_SREQ_DSREQ0 : 0;
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p_dmac->DMAC_SREQ |= (req << ul_num);
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}
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/**
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* \brief DMAC software chunk request.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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* \param ul_num Channel number.
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* \param ul_src_req Request a source transfer.
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* \param ul_dst_req Request a destination transfer.
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*/
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void dmac_soft_chunk_transfer_request(Dmac *p_dmac,
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uint32_t ul_num, uint32_t ul_src_req, uint32_t ul_dst_req)
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{
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uint32_t req;
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req = ul_src_req ? DMAC_CREQ_SCREQ0 : 0;
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req |= ul_dst_req ? DMAC_CREQ_DCREQ0 : 0;
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p_dmac->DMAC_SREQ |= (req << ul_num);
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}
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/**
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* \brief Set DMAC last transfer flag.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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* \param ul_num Channel number.
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* \param ul_src_flag Last source transfer flag.
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* \param ul_dst_flag Last destination transfer flag.
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*/
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void dmac_soft_set_last_transfer_flag(Dmac *p_dmac,
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uint32_t ul_num, uint32_t ul_src_flag, uint32_t ul_dst_flag)
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{
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uint32_t flag;
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flag = ul_src_flag ? DMAC_LAST_SLAST0 : 0;
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flag |= ul_dst_flag ? DMAC_LAST_DLAST0 : 0;
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p_dmac->DMAC_SREQ |= (flag << ul_num);
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}
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#if (SAM3XA_SERIES || SAM4E)
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/** DMAC write protect key */
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#define DMAC_WPKEY 0x50494Fu
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/**
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* \brief Enable/Disable write protect of DMAC registers.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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* \param ul_enable 1 to enable, 0 to disable.
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*/
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void dmac_set_writeprotect(Dmac *p_dmac, uint32_t ul_enable)
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{
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if (ul_enable) {
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p_dmac->DMAC_WPMR = DMAC_WPMR_WPKEY(DMAC_WPKEY) |
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DMAC_WPMR_WPEN;
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} else {
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p_dmac->DMAC_WPMR = DMAC_WPMR_WPKEY(DMAC_WPKEY);
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}
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}
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/**
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* \brief Get write protect status.
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*
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* \param p_dmac Pointer to a DMAC peripheral instance.
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*
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* \return Write protect status.
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*/
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uint32_t dmac_get_writeprotect_status(Dmac *p_dmac)
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{
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return (p_dmac->DMAC_WPSR);
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}
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#endif
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