aa7bac3cc0
Merged in Dan's thermocouple support Define serial port allocation in Pins_duet.h Fixed some leaks of OutputBuffer objects under error conditions The terminating newline character in a gcode response is now added in HandleReply
539 lines
13 KiB
C
539 lines
13 KiB
C
// ASF 3.27.0
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/**
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* \file
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*
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* \brief SPI master common service for SAM.
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*
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* Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/**
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#ifndef _SPI_MASTER_H_
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#define _SPI_MASTER_H_
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#include "compiler.h"
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#include "status_codes.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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// Request that a NPCS peripheral NOT be connected
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#define CONFIG_SPI_NO_PERIPHERALS 0xffff
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//! Default Configuration of SPI Master Delay BCS
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#ifndef CONFIG_SPI_MASTER_DELAY_BCS
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#define CONFIG_SPI_MASTER_DELAY_BCS 0
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#endif
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//! Default Configuration of SPI Master Bits per Transfer Definition
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#ifndef CONFIG_SPI_MASTER_BITS_PER_TRANSFER
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#define CONFIG_SPI_MASTER_BITS_PER_TRANSFER SPI_CSR_BITS_8_BIT
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#endif
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//! Default Configuration of SPI Master Delay BCT
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#ifndef CONFIG_SPI_MASTER_DELAY_BCT
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#define CONFIG_SPI_MASTER_DELAY_BCT 0
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#endif
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//! Default Configuration of SPI Master Delay BS
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#ifndef CONFIG_SPI_MASTER_DELAY_BS
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#define CONFIG_SPI_MASTER_DELAY_BS 0
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#endif
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//! Default Configuration of SPI Master Dummy Field
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#ifndef CONFIG_SPI_MASTER_DUMMY
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#define CONFIG_SPI_MASTER_DUMMY 0xFF
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#endif
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//! @}
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#if defined(USE_SAM3X_DMAC)
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#include "dmac.h"
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#include "pmc.h"
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#endif
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/**
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* \brief Clock phase.
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*/
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#define SPI_CPHA (1 << 0)
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/**
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* \brief Clock polarity.
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*/
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#define SPI_CPOL (1 << 1)
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/**
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* \brief SPI mode 0.
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*/
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#define SPI_MODE_0 0
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/**
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* \brief SPI mode 1.
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*/
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#define SPI_MODE_1 (SPI_CPHA)
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/**
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* \brief SPI mode 2.
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*/
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#define SPI_MODE_2 (SPI_CPOL)
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/**
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* \brief SPI mode 3.
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*/
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#define SPI_MODE_3 (SPI_CPOL | SPI_CPHA)
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/** Time-out value (number of attempts). */
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#define SPI_TIMEOUT 15000
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/** Status codes used by the SPI driver. */
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typedef enum
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{
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SPI_ERROR = -1,
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SPI_OK = 0,
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SPI_ERROR_TIMEOUT = 1,
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SPI_ERROR_ARGUMENT,
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SPI_ERROR_OVERRUN,
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SPI_ERROR_MODE_FAULT,
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SPI_ERROR_OVERRUN_AND_MODE_FAULT
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} spi_status_t;
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/** SPI Chip Select behavior modes while transferring. */
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typedef enum spi_cs_behavior {
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/** CS does not rise until a new transfer is requested on different chip
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select. */
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SPI_CS_KEEP_LOW = SPI_CSR_CSAAT,
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/** CS rises if there is no more data to transfer. */
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SPI_CS_RISE_NO_TX = 0,
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/** CS is de-asserted systematically during a time DLYBCS. */
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SPI_CS_RISE_FORCED = SPI_CSR_CSNAAT
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} spi_cs_behavior_t;
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#ifndef SPI_TYPE_DEFS
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#define SPI_TYPE_DEFS
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//! SPI Flags Definition
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typedef uint8_t spi_flags_t;
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//! Board SPI Select Id Definition
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typedef uint32_t board_spi_select_id_t;
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#endif
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//! \brief Polled SPI device definition.
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struct spi_device {
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//! Board specific select id
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board_spi_select_id_t id;
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uint8_t cs;
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uint8_t bits;
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};
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void spi_set_peripheral_chip_select_value(Spi *p_spi, uint32_t ul_value);
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void spi_set_delay_between_chip_select(Spi *p_spi, uint32_t ul_delay);
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void spi_set_baudrate_div(Spi *p_spi, uint32_t ul_pcs_ch,
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uint8_t uc_baudrate_divider);
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void spi_set_transfer_delay(Spi *p_spi, uint32_t ul_pcs_ch,
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uint8_t uc_dlybs, uint8_t uc_dlybct);
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/** \brief Initialize the SPI in master mode.
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*
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* \param p_spi Base address of the SPI instance.
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*
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*/
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extern void spi_master_init(Spi *p_spi, uint32_t ul_cs_pin, uint32_t ul_npcs_pin);
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/**
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* \brief Set up an SPI device.
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*
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* The returned device descriptor structure must be passed to the driver
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* whenever that device should be used as current slave device.
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*
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* \param p_spi Base address of the SPI instance.
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* \param device Pointer to SPI device struct that should be initialized.
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* \param flags SPI configuration flags. Common flags for all
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* implementations are the SPI modes SPI_MODE_0 ...
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* SPI_MODE_3.
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* \param baud_rate Baud rate for communication with slave device in Hz.
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* \param sel_id Board specific select id.
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*/
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extern void spi_master_setup_device(Spi *p_spi, const struct spi_device *device,
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spi_flags_t flags, uint32_t baud_rate, board_spi_select_id_t sel_id);
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/**
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* \brief Select the given device on the SPI bus.
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*
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* Set device specific setting and call board chip select.
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*
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* \param p_spi Base address of the SPI instance.
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* \param device SPI device.
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*
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*/
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extern void spi_select_device(Spi *p_spi, const struct spi_device *device);
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/**
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* \brief Deselect the given device on the SPI bus.
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*
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* Call board chip deselect.
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*
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* \param p_spi Base address of the SPI instance.
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* \param device SPI device.
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*
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* \pre SPI device must be selected with spi_select_device() first.
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*/
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extern void spi_deselect_device(Spi *p_spi, const struct spi_device *device);
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/**
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* \brief Send a sequence of bytes to an SPI device.
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*
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* Received bytes on the SPI bus are discarded.
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*
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* \param p_spi Base address of the SPI instance.
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* \param data Data buffer to write.
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* \param len Length of data to be written.
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*
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* \pre SPI device must be selected with spi_select_device() first.
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*/
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extern status_code_t spi_write_packet(Spi *p_spi, const uint8_t *data,
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size_t len);
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/**
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* \brief Check if all transmissions are ready.
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*
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* \param p_spi Pointer to an SPI instance.
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*
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* \retval 1 if transmissions are complete.
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* \retval 0 if transmissions are not complete.
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*/
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static inline uint32_t spi_is_tx_ready(Spi *p_spi)
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{
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if (p_spi->SPI_SR & SPI_SR_TDRE) {
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return 1;
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} else {
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return 0;
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}
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}
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/**
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* \brief Check if all transmissions are complete.
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*
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* \param p_spi Pointer to an SPI instance.
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*
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* \retval 1 if transmissions are complete.
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* \retval 0 if transmissions are not complete.
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*/
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static inline uint32_t spi_is_tx_empty(Spi *p_spi)
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{
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if (p_spi->SPI_SR & SPI_SR_TXEMPTY) {
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return 1;
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} else {
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return 0;
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}
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}
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/**
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* \brief Check if all receptions are ready.
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*
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* \param p_spi Pointer to an SPI instance.
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*
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* \return 1 if the SPI Receiver is ready, otherwise 0.
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*/
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static inline uint32_t spi_is_rx_ready(Spi *p_spi)
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{
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if ((p_spi->SPI_SR & (SPI_SR_RDRF | SPI_SR_TXEMPTY))
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== (SPI_SR_RDRF | SPI_SR_TXEMPTY)) {
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return 1;
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} else {
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return 0;
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}
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}
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/** \brief Get one data to a SPI peripheral.
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*
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* \param p_spi Base address of the SPI instance.
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* \return The data byte
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*
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*/
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static inline status_code_t spi_get(Spi *p_spi, uint8_t *b)
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{
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// wait for transmit register empty
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uint32_t timeout = SPI_TIMEOUT;
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while (!spi_is_tx_ready(p_spi)) {
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if (--timeout == 0) {
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return ERR_TMO;
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}
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}
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// write dummy byte with address and end transmission flag
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p_spi->SPI_TDR = 0x000000FF | SPI_TDR_LASTXFER;
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// wait for receive register
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timeout = SPI_TIMEOUT;
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while (!spi_is_rx_ready(p_spi)) {
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if (--timeout == 0) {
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return ERR_TMO;
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}
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}
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// get byte from receive register
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*b = (uint8_t)p_spi->SPI_RDR;
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return STATUS_OK;
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// return (p_spi->SPI_RDR & SPI_RDR_RD_Msk);
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}
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/** \brief Receive one byte from an SPI device.
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*
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* \param p_spi Base address of the SPI instance.
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* \param data Data to read.
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*
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*/
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#define spi_read_single(p,d) spi_get(p,d)
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//static inline status_code_t spi_read_single(Spi *p_spi, uint8_t *data)
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//{
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// return spi_get(p_spi, data);
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//}
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/**
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* \brief Receive a sequence of bytes from an SPI device.
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*
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* All bytes sent out on SPI bus are sent as value 0xff.
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*
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* \param p_spi Base address of the SPI instance.
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* \param data Data buffer to read.
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* \param len Length of data to be read.
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*
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* \pre SPI device must be selected with spi_select_device() first.
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*/
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extern status_code_t spi_read_packet(Spi *p_spi, uint8_t *data, size_t len);
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/**
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* \brief Put one data to a SPI peripheral.
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*
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* \param p_spi Base address of the SPI instance.
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* \param data The data byte to be loaded
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*
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*/
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static inline status_code_t spi_put(Spi *p_spi, uint8_t data)
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{
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// p_spi->SPI_TDR = SPI_TDR_TD(data);
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// wait for transmit register empty
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uint32_t timeout = SPI_TIMEOUT;
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while (!spi_is_tx_ready(p_spi)) {
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if (!timeout--)
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{
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return ERR_TMO;
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}
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}
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// write byte with address and end transmission flag
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p_spi->SPI_TDR = (uint32_t)data | SPI_TDR_LASTXFER;
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// wait for receive register
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timeout = SPI_TIMEOUT;
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while (!spi_is_rx_ready(p_spi)) {
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if (--timeout == 0) {
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return ERR_TMO;
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}
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}
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// clear status
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p_spi->SPI_RDR;
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return STATUS_OK;
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}
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/** \brief Write one byte to an SPI device.
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*
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* \param p_spi Base address of the SPI instance.
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* \param data Data to write.
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*
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*/
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#define spi_write_single(p,d) spi_put(p,d)
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//static inline status_code_t spi_write_single(Spi *p_spi, uint8_t data)
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//{
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// return spi_put(p_spi, (uint16_t)data);
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//}
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/**
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* \brief Test if the SPI is enabled.
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*
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* \param p_spi Pointer to an SPI instance.
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*
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* \return 1 if the SPI is enabled, otherwise 0.
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*/
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static inline uint32_t spi_is_enabled(Spi *p_spi)
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{
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if (p_spi->SPI_SR & SPI_SR_SPIENS) {
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return 1;
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} else {
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return 0;
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}
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}
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/**
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* \brief Enable SPI.
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*
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* \param p_spi Pointer to an SPI instance.
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*/
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static inline void spi_enable(Spi *p_spi)
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{
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p_spi->SPI_CR = SPI_CR_SPIEN;
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}
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/**
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* \brief Disable SPI.
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*
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* \note CS is de-asserted, which indicates that the last data is done, and user
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* should check TX_EMPTY before disabling SPI.
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*
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* \param p_spi Pointer to an SPI instance.
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*/
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static inline void spi_disable(Spi *p_spi)
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{
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p_spi->SPI_CR = SPI_CR_SPIDIS;
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}
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/**
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* \brief Reset SPI and set it to Slave mode.
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*
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* \param p_spi Pointer to an SPI instance.
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*/
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static inline void spi_reset(Spi *p_spi)
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{
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p_spi->SPI_CR = SPI_CR_SWRST;
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}
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/**
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* \brief Set SPI to Master mode.
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*
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* \param p_spi Pointer to an SPI instance.
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*/
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static inline void spi_set_master_mode(Spi *p_spi)
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{
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p_spi->SPI_MR |= SPI_MR_MSTR;
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}
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/**
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* \brief Disable Mode Fault Detection.
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*
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* \param p_spi Pointer to an SPI instance.
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*/
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static inline void spi_disable_mode_fault_detect(Spi *p_spi)
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{
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p_spi->SPI_MR |= SPI_MR_MODFDIS;
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}
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/**
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* \brief Disable loopback mode.
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*
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* \param p_spi Pointer to an SPI instance.
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*/
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static inline void spi_disable_loopback(Spi *p_spi)
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{
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p_spi->SPI_MR &= (~SPI_MR_LLB);
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}
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/**
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* \brief Set Fixed Peripheral Select.
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* Peripheral Chip Select is controlled by SPI_MR.
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*
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* \param p_spi Pointer to an SPI instance.
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*/
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static inline void spi_set_fixed_peripheral_select(Spi *p_spi)
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{
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p_spi->SPI_MR &= (~SPI_MR_PS);
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}
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/**
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* \brief Disable Peripheral Select Decode.
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*
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* \param p_spi Pointer to an SPI instance.
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*/
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static inline void spi_disable_peripheral_select_decode(Spi *p_spi)
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{
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p_spi->SPI_MR &= (~SPI_MR_PCSDEC);
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}
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/**
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* \brief Get Peripheral Select Decode mode.
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*
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* \param p_spi Pointer to an SPI instance.
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*
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* \return 1 for decode mode, 0 for direct mode.
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*/
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static inline uint32_t spi_get_peripheral_select_decode_setting(Spi *p_spi)
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{
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if (p_spi->SPI_MR & SPI_MR_PCSDEC) {
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return 1;
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} else {
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return 0;
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}
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}
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#if defined(USE_SAM3X_DMAC)
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#define SPI_TX_IDX 1 // DMAC HW interface id for SPI TX (Table 22-2. DMA Controller)
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#define SPI_RX_IDX 2 // DMAC HW interface id for SPI RX (Table 22-2. DMA Controller)
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void spi_start_transmit_dma(Dmac *p_dmac, Spi *p_spi, uint32_t ul_num,
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const void *src, uint32_t nb_bytes);
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void spi_start_receive_dma(Dmac *p_dmac, Spi *p_spi, uint32_t ul_num,
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const void *dest, uint32_t nb_bytes);
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static inline uint32_t spi_get_peripheral_chip_select_value(Spi *p_spi)
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{
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// return 3 & ((p_spi->SPI_MR & SPI_MR_PCS_Msk) >> SPI_MR_PCS_Pos);
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return 3 & (p_spi->SPI_MR >> SPI_MR_PCS_Pos);
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}
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static inline uint32_t spi_get_clock_divisor(Spi *p_spi)
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{
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uint32_t ul_pcs_ch = spi_get_peripheral_chip_select_value(p_spi);
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if (ul_pcs_ch > 3) return 255;
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return (p_spi->SPI_CSR[ul_pcs_ch] & SPI_CSR_SCBR_Msk) >> SPI_CSR_SCBR_Pos;
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}
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif // _SPI_MASTER_H_
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