f5c4bdc770
Added timeout to output buffers destined for USB Fixed bugs in thermocouple code Reallocated thermocouple pin numbers Made Roland mill and inkjet support conditional and normally disabled Fixed issue with thermocouple code messing up the timekeeping system, which was suspected of causing the network to be unreliable Added support for M577 (thanks chrishamm)
615 lines
17 KiB
C
615 lines
17 KiB
C
// ASF 3.27.0
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/**
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* \file
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*
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* \brief SPI master common service for SAM.
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*
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* Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/**
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#include "Arduino.h"
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#include "compiler.h"
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#include "spi_master.h"
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#include "variant.h"
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#ifndef F_CPU
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#define F_CPU 84000000UL
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#endif
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#ifndef MOSI_PIN
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#define MOSI_PIN MOSI
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#endif
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#ifndef MISO_PIN
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#define MISO_PIN MISO
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#endif
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#ifndef SCK_PIN
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#define SCK_PIN SCK
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#endif
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#define WRITE(pin, v) do{if(v) {g_APinDescription[pin].pPort->PIO_SODR = g_APinDescription[pin].ulPin;} else {g_APinDescription[pin].pPort->PIO_CODR = g_APinDescription[pin].ulPin; }}while(0)
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/**
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* \brief Max number when the chip selects are connected to a 4- to 16-bit decoder.
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*/
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#define MAX_NUM_WITH_DECODER 0x10
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/**
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* \brief Max number when the chip selects are directly connected to peripheral device.
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*/
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#define MAX_NUM_WITHOUT_DECODER 0x04
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/**
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* \brief Max number when the chip selects are directly connected to peripheral device.
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*/
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#define NONE_CHIP_SELECT_ID 0x0f
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/**
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* \brief The default chip select id.
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*/
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#define DEFAULT_CHIP_ID 1
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/**
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* \brief Issue a LASTXFER command.
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* The next transfer is the last transfer and after that CS is de-asserted.
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*
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* \param p_spi Pointer to an SPI instance.
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*/
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static inline void spi_set_lastxfer(Spi *p_spi)
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{
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p_spi->SPI_CR = SPI_CR_LASTXFER;
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}
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/**
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* \brief Configure CS behavior for SPI transfer (\ref spi_cs_behavior_t).
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*
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* \param p_spi Pointer to an SPI instance.
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* \param ul_pcs_ch Peripheral Chip Select channel (0~3).
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* \param ul_cs_behavior Behavior of the Chip Select after transfer.
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*/
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void spi_configure_cs_behavior(Spi *p_spi, uint32_t ul_pcs_ch,
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uint32_t ul_cs_behavior)
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{
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if (ul_cs_behavior == SPI_CS_RISE_FORCED) {
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p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_CSAAT);
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p_spi->SPI_CSR[ul_pcs_ch] |= SPI_CSR_CSNAAT;
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} else if (ul_cs_behavior == SPI_CS_RISE_NO_TX) {
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p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_CSAAT);
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p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_CSNAAT);
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} else if (ul_cs_behavior == SPI_CS_KEEP_LOW) {
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p_spi->SPI_CSR[ul_pcs_ch] |= SPI_CSR_CSAAT;
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}
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}
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/**
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* \brief Set number of bits per transfer.
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*
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* \param p_spi Pointer to an SPI instance.
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* \param ul_pcs_ch Peripheral Chip Select channel (0~3).
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* \param ul_bits Number of bits (8~16), use the pattern defined
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* in the device header file.
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*/
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void spi_set_bits_per_transfer(Spi *p_spi, uint32_t ul_pcs_ch,
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uint32_t ul_bits)
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{
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p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_BITS_Msk);
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p_spi->SPI_CSR[ul_pcs_ch] |= ul_bits;
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}
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/**
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* \brief Configure timing for SPI transfer.
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*
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* \param p_spi Pointer to an SPI instance.
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* \param ul_pcs_ch Peripheral Chip Select channel (0~3).
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* \param uc_dlybs Delay before SPCK (in number of MCK clocks).
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* \param uc_dlybct Delay between consecutive transfers (in number of MCK clocks
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).
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*/
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void spi_set_transfer_delay(Spi *p_spi, uint32_t ul_pcs_ch,
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uint8_t uc_dlybs, uint8_t uc_dlybct)
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{
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p_spi->SPI_CSR[ul_pcs_ch] &= ~(SPI_CSR_DLYBS_Msk | SPI_CSR_DLYBCT_Msk);
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p_spi->SPI_CSR[ul_pcs_ch] |= SPI_CSR_DLYBS(uc_dlybs)
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| SPI_CSR_DLYBCT(uc_dlybct);
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}
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/**
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* \brief Set clock default state.
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*
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* \param p_spi Pointer to an SPI instance.
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* \param ul_pcs_ch Peripheral Chip Select channel (0~3).
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* \param ul_polarity Default clock state is logical one(high)/zero(low).
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*/
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void spi_set_clock_polarity(Spi *p_spi, uint32_t ul_pcs_ch,
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uint32_t ul_polarity)
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{
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if (ul_polarity) {
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p_spi->SPI_CSR[ul_pcs_ch] |= SPI_CSR_CPOL;
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} else {
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p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_CPOL);
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}
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}
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/**
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* \brief Set Data Capture Phase.
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*
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* \param p_spi Pointer to an SPI instance.
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* \param ul_pcs_ch Peripheral Chip Select channel (0~3).
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* \param ul_phase Data capture on the rising/falling edge of clock.
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*/
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void spi_set_clock_phase(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_phase)
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{
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if (ul_phase) {
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p_spi->SPI_CSR[ul_pcs_ch] |= SPI_CSR_NCPHA;
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} else {
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p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_NCPHA);
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}
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}
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/** \brief Initialize the SPI in master mode.
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*
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* \param p_spi Base address of the SPI instance.
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*
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*/
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void spi_master_init(Spi *p_spi, int ul_cs_pin, int ul_npcs_pin)
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{
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static bool init_comms = true;
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if (init_comms)
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{
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PIO_Configure(
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g_APinDescription[SCK_PIN].pPort,
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g_APinDescription[SCK_PIN].ulPinType,
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g_APinDescription[SCK_PIN].ulPin,
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g_APinDescription[SCK_PIN].ulPinConfiguration);
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PIO_Configure(
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g_APinDescription[MOSI_PIN].pPort,
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g_APinDescription[MOSI_PIN].ulPinType,
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g_APinDescription[MOSI_PIN].ulPin,
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g_APinDescription[MOSI_PIN].ulPinConfiguration);
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PIO_Configure(
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g_APinDescription[MISO_PIN].pPort,
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g_APinDescription[MISO_PIN].ulPinType,
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g_APinDescription[MISO_PIN].ulPin,
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g_APinDescription[MISO_PIN].ulPinConfiguration);
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pmc_enable_periph_clk(ID_SPI0);
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spi_reset(p_spi);
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// set master mode, peripheral select, disable fault detection
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SPI_Configure(p_spi, ID_SPI0,
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SPI_MR_MSTR | // Master mode
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SPI_MR_MODFDIS); // Disable mode fault detection
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SPI_Enable(p_spi);
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init_comms = false;
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}
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if (ul_npcs_pin >= 0)
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{
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// Connect the NPCS pin as a PIO peripheral and assert it HIGH
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PIO_Configure(
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g_APinDescription[ul_npcs_pin].pPort,
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g_APinDescription[ul_npcs_pin].ulPinType,
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g_APinDescription[ul_npcs_pin].ulPin,
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g_APinDescription[ul_npcs_pin].ulPinConfiguration);
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WRITE(ul_npcs_pin, HIGH);
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}
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if (ul_cs_pin >= 0)
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{
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PIO_Configure(
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g_APinDescription[ul_cs_pin].pPort,
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PIO_OUTPUT_1,
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g_APinDescription[ul_cs_pin].ulPin,
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g_APinDescription[ul_cs_pin].ulPinConfiguration);
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WRITE(ul_cs_pin, HIGH);
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}
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#if defined(USE_SAM3X_DMAC)
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pmc_enable_periph_clk(ID_DMAC);
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dmac_disable(DMAC);
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dmac_set_priority_mode(DMAC, DMAC_GCFG_ARB_CFG_FIXED);
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dmac_enable(DMAC);
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#endif
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// spi_enable_clock(p_spi);
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// spi_reset(p_spi);
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// spi_set_master_mode(p_spi);
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// spi_disable_mode_fault_detect(p_spi);
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// spi_disable_loopback(p_spi);
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// spi_set_peripheral_chip_select_value(p_spi, DEFAULT_CHIP_ID);
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// spi_set_fixed_peripheral_select(p_spi);
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// spi_disable_peripheral_select_decode(p_spi);
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// spi_set_delay_between_chip_select(p_spi, CONFIG_SPI_MASTER_DELAY_BCS);
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// SPI_Enable(p_spi);
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}
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/**
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* \brief Calculate the baudrate divider.
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*
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* \param baudrate Baudrate value.
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* \param mck SPI module input clock frequency (MCK clock, Hz).
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*
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* \return Divider or error code.
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* \retval > 0 Success.
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* \retval < 0 Error.
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*/
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int16_t spi_calc_baudrate_div(uint32_t baud_rate, uint32_t mck)
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{
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int16_t baud_div = div_ceil(mck, baud_rate);
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/* The value of baud_div is from 1 to 255 in the SCBR field. */
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if (baud_div <= 0)
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baud_div = 10;
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else if (baud_div > 255)
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baud_div = 255;
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return baud_div;
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}
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/**
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* \brief Set up an SPI device.
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*
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* The returned device descriptor structure must be passed to the driver
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* whenever that device should be used as current slave device.
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*
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* \param p_spi Base address of the SPI instance.
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* \param device Pointer to SPI device struct that should be initialized.
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* \param flags SPI configuration flags. Common flags for all
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* implementations are the SPI modes SPI_MODE_0 ...
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* SPI_MODE_3.
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* \param baud_rate Baud rate for communication with slave device in Hz.
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* \param sel_id Board specific select id.
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*/
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void spi_master_setup_device(Spi *p_spi, const struct spi_device *device,
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spi_flags_t flags, uint32_t baud_rate, board_spi_select_id_t sel_id)
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{
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/* avoid Cppcheck Warning */
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UNUSED(sel_id);
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UNUSED(flags);
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spi_reset(p_spi);
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SPI_Configure(p_spi, ID_SPI0,
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SPI_MR_MSTR | // Master mode
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SPI_MR_MODFDIS); // Disable mode fault detection
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// Set SPI mode 0, clock, select not active after transfer
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// with delay between transfers
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int16_t baud_div = spi_calc_baudrate_div(baud_rate, F_CPU);
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SPI_ConfigureNPCS(p_spi, device->id,
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SPI_CSR_NCPHA | // Data capture on rising edge of clock
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SPI_CSR_CSAAT | // CS behavior == SPI_CS_KEEP_LOW
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SPI_CSR_SCBR(baud_div) | // Baud rate
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device->bits | // Transfer bit width
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SPI_CSR_DLYBCT(1)); // Transfer delay
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SPI_Enable(p_spi);
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// spi_set_bits_per_transfer(p_spi, device->id, device->bits);
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// spi_set_transfer_delay(p_spi, device->id, CONFIG_SPI_MASTER_DELAY_BS,
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// CONFIG_SPI_MASTER_DELAY_BCT);
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// spi_set_baudrate_div(p_spi, device->id,
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// spi_calc_baudrate_div(baud_rate, F_CPU));
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// spi_configure_cs_behavior(p_spi, device->id, SPI_CS_KEEP_LOW);
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// spi_set_clock_polarity(p_spi, device->id, flags >> 1);
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// spi_set_clock_phase(p_spi, device->id, ((flags & 0x1) ^ 0x1));
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}
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/**
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* \brief Select the given device on the SPI bus.
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*
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* Set device specific setting and call board chip select.
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*
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* \param p_spi Base address of the SPI instance.
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* \param device SPI device.
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*
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*/
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void spi_select_device(Spi *p_spi, const struct spi_device *device)
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{
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if (spi_get_peripheral_select_decode_setting(p_spi)) {
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if (device->id < MAX_NUM_WITH_DECODER) {
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spi_set_peripheral_chip_select_value(p_spi, device->id);
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}
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} else {
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if (device->id < MAX_NUM_WITHOUT_DECODER) {
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spi_set_peripheral_chip_select_value(p_spi, (~(1 << device->id)));
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}
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}
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// Enable the CS line
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WRITE(device->cs, LOW);
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}
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/**
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* \brief Deselect the given device on the SPI bus.
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*
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* Call board chip deselect.
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*
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* \param p_spi Base address of the SPI instance.
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* \param device SPI device.
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*
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* \pre SPI device must be selected with spi_select_device() first.
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*/
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void spi_deselect_device(Spi *p_spi, const struct spi_device *device)
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{
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uint32_t timeout = SPI_TIMEOUT;
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while (!spi_is_tx_empty(p_spi)) {
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if (!timeout--) {
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return;
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}
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}
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// Last transfer, so de-assert the current NPCS if CSAAT is set.
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spi_set_lastxfer(p_spi);
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// Disable the CS line
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WRITE(device->cs, HIGH);
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// Assert all lines; no peripheral is selected.
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spi_set_peripheral_chip_select_value(p_spi, NONE_CHIP_SELECT_ID);
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}
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/**
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* \brief Send a sequence of bytes to an SPI device.
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*
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* Received bytes on the SPI bus are discarded.
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*
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* \param p_spi Base address of the SPI instance.
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* \param data Data buffer to write.
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* \param len Length of data to be written.
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*
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* \pre SPI device must be selected with spi_select_device() first.
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*/
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status_code_t spi_write_packet(Spi *p_spi, const uint8_t *data, size_t len)
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{
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if (len == 0)
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return STATUS_OK;
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for (size_t i = 0; i < len-1; i++)
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{
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uint32_t timeout = SPI_TIMEOUT;
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while (!spi_is_tx_ready(p_spi)) {
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if (!timeout--) {
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return ERR_TMO;
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}
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}
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p_spi->SPI_TDR = (uint32_t)data[i];
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while (!spi_is_rx_ready(p_spi)) {
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if (!timeout--) {
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return ERR_TMO;
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}
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}
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p_spi->SPI_RDR;
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}
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return spi_write_single(p_spi, data[len-1]);
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}
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/**
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* \brief Receive a sequence of bytes from an SPI device.
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*
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* All bytes sent out on SPI bus are sent as value 0.
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*
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* \param p_spi Base address of the SPI instance.
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* \param data Data buffer to read.
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* \param len Length of data to be read.
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*
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* \pre SPI device must be selected with spi_select_device() first.
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*/
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status_code_t spi_read_packet(Spi *p_spi, uint8_t *data, size_t len)
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{
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if (len-- == 0)
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return STATUS_OK;
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for (uint16_t i = 0; i < len; i++)
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{
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uint32_t timeout = SPI_TIMEOUT;
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while (!spi_is_tx_ready(p_spi)) {
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if (!timeout--) {
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return ERR_TMO;
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}
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}
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p_spi->SPI_TDR = 0x000000FF;
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timeout = SPI_TIMEOUT;
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while (!spi_is_rx_ready(p_spi)) {
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if (!timeout--) {
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return ERR_TMO;
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}
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}
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data[i] = p_spi->SPI_RDR;
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}
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return spi_read_single(p_spi, &data[len]);
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}
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/**
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* \brief Set Peripheral Chip Select (PCS) value.
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*
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* \param p_spi Pointer to an SPI instance.
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* \param ul_value Peripheral Chip Select value.
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* If PCS decode mode is not used, use \ref spi_get_pcs to build
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* the value to use.
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* On reset the decode mode is not enabled.
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* The decode mode can be enabled/disabled by follow functions:
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* \ref spi_enable_peripheral_select_decode,
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* \ref spi_disable_peripheral_select_decode.
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*/
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void spi_set_peripheral_chip_select_value(Spi *p_spi, uint32_t ul_value)
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{
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p_spi->SPI_MR &= (~SPI_MR_PCS_Msk);
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p_spi->SPI_MR |= SPI_MR_PCS(ul_value);
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}
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|
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/**
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* \brief Set delay between chip selects (in number of MCK clocks).
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* If DLYBCS <= 6, 6 MCK clocks will be inserted by default.
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*
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* \param p_spi Pointer to an SPI instance.
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* \param ul_delay Delay between chip selects (in number of MCK clocks).
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|
*/
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void spi_set_delay_between_chip_select(Spi *p_spi, uint32_t ul_delay)
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|
{
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p_spi->SPI_MR &= (~SPI_MR_DLYBCS_Msk);
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p_spi->SPI_MR |= SPI_MR_DLYBCS(ul_delay);
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}
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|
|
|
/**
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|
* \brief Set Serial Clock Baud Rate divider value (SCBR).
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|
*
|
|
* \param p_spi Pointer to an SPI instance.
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|
* \param ul_pcs_ch Peripheral Chip Select channel (0~3).
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|
* \param uc_baudrate_divider Baudrate divider from MCK.
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|
*/
|
|
void spi_set_baudrate_div(Spi *p_spi, uint32_t ul_pcs_ch,
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|
uint8_t uc_baudrate_divider)
|
|
{
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|
p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_SCBR_Msk);
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|
p_spi->SPI_CSR[ul_pcs_ch] |= SPI_CSR_SCBR(uc_baudrate_divider);
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|
}
|
|
|
|
#if defined(USE_SAM3X_DMAC)
|
|
|
|
void spi_start_transmit_dma(Dmac *p_dmac, Spi *p_spi, uint32_t ul_num,
|
|
const void *src, uint32_t nb_bytes)
|
|
{
|
|
static uint8_t ff = 0xFF;
|
|
uint32_t cfg, src_incr = DMAC_CTRLB_SRC_INCR_INCREMENTING;
|
|
dma_transfer_descriptor_t desc;
|
|
|
|
// Send 0xFF repeatedly if src is NULL
|
|
if (!src) {
|
|
src = &ff;
|
|
src_incr = DMAC_CTRLB_SRC_INCR_FIXED;
|
|
}
|
|
|
|
// Disable the DMA channel prior to configuring
|
|
dmac_enable(p_dmac);
|
|
dmac_channel_disable(p_dmac, ul_num);
|
|
|
|
cfg = DMAC_CFG_SOD
|
|
| DMAC_CFG_DST_H2SEL
|
|
| DMAC_CFG_DST_PER(SPI_TX_IDX)
|
|
| DMAC_CFG_FIFOCFG_ALAP_CFG;
|
|
dmac_channel_set_configuration(p_dmac, ul_num, cfg);
|
|
|
|
// Prepare DMA transfer
|
|
desc.ul_source_addr = (uint32_t)src;
|
|
desc.ul_destination_addr = (uint32_t)&(p_spi->SPI_TDR);
|
|
desc.ul_ctrlA = DMAC_CTRLA_BTSIZE(nb_bytes)
|
|
| DMAC_CTRLA_SRC_WIDTH_BYTE
|
|
| DMAC_CTRLA_DST_WIDTH_BYTE;
|
|
desc.ul_ctrlB = DMAC_CTRLB_SRC_DSCR
|
|
| DMAC_CTRLB_DST_DSCR
|
|
| DMAC_CTRLB_FC_MEM2PER_DMA_FC
|
|
| src_incr
|
|
| DMAC_CTRLB_DST_INCR_FIXED;
|
|
|
|
// Next field is ignored, but set it anyway
|
|
desc.ul_descriptor_addr = (uint32_t)NULL;
|
|
|
|
// Finish configuring the transfer
|
|
dmac_channel_single_buf_transfer_init(p_dmac, ul_num, &desc);
|
|
|
|
// And now start the DMA transfer
|
|
dmac_channel_enable(p_dmac, ul_num);
|
|
}
|
|
|
|
void spi_start_receive_dma(Dmac *p_dmac, Spi *p_spi, uint32_t ul_num,
|
|
const void *dest, uint32_t nb_bytes)
|
|
{
|
|
uint32_t cfg;
|
|
dma_transfer_descriptor_t desc;
|
|
|
|
// clear any potential overrun error
|
|
cfg = p_spi->SPI_SR;
|
|
|
|
// Turn the DMA channel off before configuring
|
|
dmac_enable(p_dmac);
|
|
dmac_channel_disable(p_dmac, ul_num);
|
|
|
|
cfg = DMAC_CFG_SOD
|
|
| DMAC_CFG_SRC_H2SEL
|
|
| DMAC_CFG_SRC_PER(SPI_RX_IDX)
|
|
| DMAC_CFG_FIFOCFG_ASAP_CFG;
|
|
dmac_channel_set_configuration(p_dmac, ul_num, cfg);
|
|
|
|
// Prepare DMA transfer
|
|
desc.ul_source_addr = (uint32_t)&(p_spi->SPI_RDR);
|
|
desc.ul_destination_addr = (uint32_t)dest;
|
|
desc.ul_ctrlA = DMAC_CTRLA_BTSIZE(nb_bytes)
|
|
| DMAC_CTRLA_SRC_WIDTH_BYTE
|
|
| DMAC_CTRLA_DST_WIDTH_BYTE;
|
|
desc.ul_ctrlB = DMAC_CTRLB_SRC_DSCR
|
|
| DMAC_CTRLB_DST_DSCR
|
|
| DMAC_CTRLB_FC_PER2MEM_DMA_FC
|
|
| DMAC_CTRLB_SRC_INCR_FIXED
|
|
| DMAC_CTRLB_DST_INCR_INCREMENTING;
|
|
|
|
// This next field is ignored but set it anyway
|
|
desc.ul_descriptor_addr = (uint32_t)NULL;
|
|
|
|
// Finish configuring the DMA transfer
|
|
dmac_channel_single_buf_transfer_init(p_dmac, ul_num, &desc);
|
|
|
|
// And now allow the DMA transfer to begin
|
|
dmac_channel_enable(p_dmac, ul_num);
|
|
}
|
|
|
|
#endif
|
|
|
|
//! @}
|