4a1072a8e7
Merged in chrishamm's changes including OutputBuffer fix, changes to Roland pin numbers, rr_configfile support in web server, and Roland and inkjet pin numbers moved to Pins_duet.h Merged in wrangellboy's http response changes for compatibility with Edge browser Other minor changes
704 lines
18 KiB
C
704 lines
18 KiB
C
/**
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* \file
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*
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* \brief SAM4E DMA Controller (DMAC) driver.
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*
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* Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#include "dmac.h"
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#ifndef DMAC_WPMR_WPKEY_PASSWD
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# define DMAC_WPMR_WPKEY_PASSWD DMAC_WPMR_WPKEY(0x444D41u)
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#endif
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/**
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* \brief Initialize the DMA controller and disable it.
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*
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* \param[in,out] p_dmac Module hardware register base address pointer
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*/
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void dmac_init(
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Dmac *p_dmac)
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{
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dmac_disable(p_dmac);
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}
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/**
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* \brief Set the DMA priority mode.
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*
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* \param[in,out] p_dmac Module hardware register base address pointer
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* \param[in] mode \ref dmac_priority_mode_t "Priority mode"
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*/
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void dmac_set_priority_mode(
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Dmac *p_dmac,
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dmac_priority_mode_t mode)
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{
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/* Validate parameters. */
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Assert(p_dmac);
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p_dmac->DMAC_GCFG = (p_dmac->DMAC_GCFG & (~DMAC_GCFG_ARB_CFG)) | mode;
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}
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/**
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* \brief Enable the DMA Controller.
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*
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* \param[out] p_dmac Module hardware register base address pointer
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*/
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void dmac_enable(
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Dmac *p_dmac)
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{
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/* Validate parameters. */
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Assert(p_dmac);
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p_dmac->DMAC_EN = DMAC_EN_ENABLE;
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}
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/**
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* \brief Disable the DMA Controller.
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*
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* \param[in,out] p_dmac Module hardware register base address pointer
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*/
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void dmac_disable(
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Dmac *p_dmac)
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{
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/* Validate parameters. */
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Assert(p_dmac);
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p_dmac->DMAC_EN &= (~DMAC_EN_ENABLE);
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}
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/**
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* \brief Enable DMAC interrupts.
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*
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* \param[out] p_dmac Module hardware register base address pointer
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* \param[in] ul_mask A bitmask of interrupts to be enabled
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*
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* Where input parameter <i>ul_mask</i> is a bitmask containing one or more
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* of the following:
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* <table>
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* <tr>
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* <th>Parameter Value</th>
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* <th>Description</th>
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* </tr>
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* <tr><td>DMAC_EBCIER_BTC0</td><td>Channel 0 Buffer Transfer Completed</td></tr>
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* <tr><td>DMAC_EBCIER_BTC1</td><td>Channel 1 Buffer Transfer Completed</td></tr>
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* <tr><td>DMAC_EBCIER_BTC2</td><td>Channel 2 Buffer Transfer Completed</td></tr>
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* <tr><td>DMAC_EBCIER_BTC3</td><td>Channel 3 Buffer Transfer Completed</td></tr>
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* <tr><td>DMAC_EBCIER_CBTC0</td><td>Channel 0 Chained Buffer Transfer Completed</td></tr>
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* <tr><td>DMAC_EBCIER_CBTC1</td><td>Channel 1 Chained Buffer Transfer Completed</td></tr>
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* <tr><td>DMAC_EBCIER_CBTC2</td><td>Channel 2 Chained Buffer Transfer Completed</td></tr>
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* <tr><td>DMAC_EBCIER_CBTC3</td><td>Channel 3 Chained Buffer Transfer Completed</td></tr>
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* <tr><td>DMAC_EBCIER_ERR0</td><td>Channel 0 Access Error</td></tr>
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* <tr><td>DMAC_EBCIER_ERR1</td><td>Channel 1 Access Error</td></tr>
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* <tr><td>DMAC_EBCIER_ERR2</td><td>Channel 2 Access Error</td></tr>
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* <tr><td>DMAC_EBCIER_ERR3</td><td>Channel 3 Access Error</td></tr>
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* </table>
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*/
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void dmac_enable_interrupt(
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Dmac *p_dmac,
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uint32_t ul_mask)
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{
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/* Validate parameters. */
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Assert(p_dmac);
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p_dmac->DMAC_EBCIER = ul_mask;
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}
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/**
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* \brief Disable DMAC interrupts.
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*
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* \param[out] p_dmac Module hardware register base address pointer
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* \param[in] ul_mask A bitmask of interrupts to be disabled
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*
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* Where input parameter <i>ul_mask</i> is a bitmask containing one or more
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* of the following:
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* <table>
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* <tr>
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* <th>Parameter Value</th>
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* <th>Description</th>
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* </tr>
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* <tr><td>DMAC_EBCIDR_BTC0</td><td>Channel 0 Buffer Transfer Completed</td></tr>
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* <tr><td>DMAC_EBCIDR_BTC1</td><td>Channel 1 Buffer Transfer Completed</td></tr>
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* <tr><td>DMAC_EBCIDR_BTC2</td><td>Channel 2 Buffer Transfer Completed</td></tr>
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* <tr><td>DMAC_EBCIDR_BTC3</td><td>Channel 3 Buffer Transfer Completed</td></tr>
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* <tr><td>DMAC_EBCIDR_CBTC0</td><td>Channel 0 Chained Buffer Transfer Completed</td></tr>
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* <tr><td>DMAC_EBCIDR_CBTC1</td><td>Channel 1 Chained Buffer Transfer Completed</td></tr>
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* <tr><td>DMAC_EBCIDR_CBTC2</td><td>Channel 2 Chained Buffer Transfer Completed</td></tr>
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* <tr><td>DMAC_EBCIDR_CBTC3</td><td>Channel 3 Chained Buffer Transfer Completed</td></tr>
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* <tr><td>DMAC_EBCIDR_ERR0</td><td>Channel 0 Access Error</td></tr>
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* <tr><td>DMAC_EBCIDR_ERR1</td><td>Channel 1 Access Error</td></tr>
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* <tr><td>DMAC_EBCIDR_ERR2</td><td>Channel 2 Access Error</td></tr>
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* <tr><td>DMAC_EBCIDR_ERR3</td><td>Channel 3 Access Error</td></tr>
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* </table>
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*/
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void dmac_disable_interrupt(
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Dmac *p_dmac,
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uint32_t ul_mask)
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{
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/* Validate parameters. */
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Assert(p_dmac);
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p_dmac->DMAC_EBCIDR = ul_mask;
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}
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/**
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* \brief Get the DMAC Interrupt Mask.
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*
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* \param[in] p_dmac Module hardware register base address pointer
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*
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* \return DMAC Interrupt mask.
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*/
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uint32_t dmac_get_interrupt_mask(
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Dmac *p_dmac)
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{
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/* Validate parameters. */
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Assert(p_dmac);
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return p_dmac->DMAC_EBCIMR;
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}
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/**
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* \brief Get the DMAC transfer status.
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*
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* \param[in] p_dmac Module hardware register base address pointer
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*
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* \return DMAC transfer status. Refer to section called "DMAC Error,
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* Buffer Transfer and Chained Buffer Transfer Status Register" in the
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* device-specific datasheet for more information.
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*/
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uint32_t dmac_get_status(
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Dmac *p_dmac)
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{
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/* Validate parameters. */
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Assert(p_dmac);
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return p_dmac->DMAC_EBCISR;
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}
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/**
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* \brief Enable the specified DMA Channel.
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*
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* \param[out] p_dmac Module hardware register base address pointer
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* \param[in] ul_num DMA Channel number (range 0 to 3)
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*/
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void dmac_channel_enable(
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Dmac *p_dmac,
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uint32_t ul_num)
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{
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/* Validate parameters. */
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Assert(p_dmac);
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Assert(ul_num<=3);
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p_dmac->DMAC_CHER = DMAC_CHER_ENA0 << ul_num;
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}
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/**
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* \brief Disable the specified DMA Channel.
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*
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* \param[out] p_dmac Module hardware register base address pointer
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* \param[in] ul_num DMA Channel number (range 0 to 3)
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*/
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void dmac_channel_disable(
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Dmac *p_dmac,
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uint32_t ul_num)
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{
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/* Validate parameters. */
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Assert(p_dmac);
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Assert(ul_num<=3);
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p_dmac->DMAC_CHDR = DMAC_CHDR_DIS0 << ul_num;
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}
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/**
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* \brief Check if the specified DMA Channel is enabled.
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*
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* \param[in] p_dmac Module hardware register base address pointer
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* \param[in] ul_num DMA Channel number (range 0 to 3)
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*
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* \return The DMA Channel's enable/disable status.
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* \retval 0 DMA Channel is disabled
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* \retval 1 DMA Channel is enabled
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*/
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uint32_t dmac_channel_is_enable(
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Dmac *p_dmac,
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uint32_t ul_num)
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{
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/* Validate parameters. */
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Assert(p_dmac);
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Assert(ul_num<=3);
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if (p_dmac->DMAC_CHSR & (DMAC_CHSR_ENA0 << ul_num)) {
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return 1;
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} else {
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return 0;
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}
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}
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/**
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* \brief Suspend the specified DMA Channel and its current context.
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*
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* \param[out] p_dmac Module hardware register base address pointer
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* \param[in] ul_num DMA Channel number (range 0 to 3)
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*/
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void dmac_channel_suspend(
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Dmac *p_dmac,
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uint32_t ul_num)
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{
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/* Validate parameters. */
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Assert(p_dmac);
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Assert(ul_num<=3);
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p_dmac->DMAC_CHER = DMAC_CHER_SUSP0 << ul_num;
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}
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/**
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* \brief Resume the specified DMA Channel transfer (restoring its context).
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*
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* \param[out] p_dmac Module hardware register base address pointer
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* \param[in] ul_num DMA Channel number (range 0 to 3)
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*/
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void dmac_channel_resume(
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Dmac *p_dmac,
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uint32_t ul_num)
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{
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/* Validate parameters. */
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Assert(p_dmac);
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Assert(ul_num<=3);
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p_dmac->DMAC_CHDR = DMAC_CHDR_RES0 << ul_num;
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}
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/**
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* \brief Resume the specified DMA Channel from an automatic stall state.
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*
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* \param[out] p_dmac Module hardware register base address pointer
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* \param[in] ul_num DMA Channel number (range 0 to 3)
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*/
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void dmac_channel_keep(
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Dmac *p_dmac,
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uint32_t ul_num)
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{
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/* Validate parameters. */
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Assert(p_dmac);
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Assert(ul_num<=3);
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p_dmac->DMAC_CHER = DMAC_CHER_KEEP0 << ul_num;
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}
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/**
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* \brief Get the DMAC Channel handler status.
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*
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* \param[in] p_dmac Module hardware register base address pointer
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*
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* \return DMAC Channel handler status register. Refer to the section called
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* "DMAC Channel Handler Status Register" in the device-specific datasheet for more
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* information.
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*/
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uint32_t dmac_channel_get_status(Dmac *p_dmac)
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{
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/* Validate parameters. */
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Assert(p_dmac);
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return p_dmac->DMAC_CHSR;
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}
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/**
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* \brief Set the DMA source address of the specified DMA Channel.
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*
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* \param[out] p_dmac Module hardware register base address pointer
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* \param[in] ul_num DMA Channel number (range 0 to 3)
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* \param[in] ul_addr Source address
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*
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* \note This register must be aligned with the source transfer width.
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*/
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void dmac_channel_set_source_addr(
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Dmac *p_dmac,
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uint32_t ul_num,
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uint32_t ul_addr)
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{
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/* Validate parameters. */
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Assert(p_dmac);
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Assert(ul_num<=3);
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p_dmac->DMAC_CH_NUM[ul_num].DMAC_SADDR = ul_addr;
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}
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/**
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* \brief Set the DMA destination address of the specified DMA Channel.
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*
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* \param[out] p_dmac Module hardware register base address pointer
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* \param[in] ul_num DMA Channel number (range 0 to 3)
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* \param[in] ul_addr Destination address
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*
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* \note This register must be aligned with the source transfer width.
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*/
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void dmac_channel_set_destination_addr(
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Dmac *p_dmac,
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uint32_t ul_num,
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uint32_t ul_addr)
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{
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/* Validate parameters. */
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Assert(p_dmac);
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Assert(ul_num<=3);
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p_dmac->DMAC_CH_NUM[ul_num].DMAC_DADDR = ul_addr;
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}
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/**
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* \brief Set the DMA descriptor address of the specified DMA Channel.
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*
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* \param[out] p_dmac Module hardware register base address pointer
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* \param[in] ul_num DMA Channel number (range 0 to 3)
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* \param[in] ul_desc Descriptor address
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*/
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void dmac_channel_set_descriptor_addr(
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Dmac *p_dmac,
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uint32_t ul_num,
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uint32_t ul_desc)
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{
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/* Validate parameters. */
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Assert(p_dmac);
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Assert(ul_num<=3);
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p_dmac->DMAC_CH_NUM[ul_num].DMAC_DSCR = ul_desc;
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}
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/**
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* \brief Set the DMA control A of the specified DMA Channel.
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*
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* \param[out] p_dmac Module hardware register base address pointer
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* \param[in] ul_num DMA Channel number (range 0 to 3)
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* \param[in] ul_ctrlA Configuration of control A register
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*/
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void dmac_channel_set_ctrlA(
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Dmac *p_dmac,
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uint32_t ul_num,
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uint32_t ul_ctrlA)
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{
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/* Validate parameters. */
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Assert(p_dmac);
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Assert(ul_num<=3);
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p_dmac->DMAC_CH_NUM[ul_num].DMAC_CTRLA = ul_ctrlA;
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}
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/**
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* \brief Set the DMA control B of the specified DMA Channel.
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*
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* \param[out] p_dmac Module hardware register base address pointer
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* \param[in] ul_num DMA Channel number (range 0 to 3)
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* \param[in] ul_ctrlB Configuration of control B register
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*/
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void dmac_channel_set_ctrlB(
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Dmac *p_dmac,
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uint32_t ul_num,
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uint32_t ul_ctrlB)
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{
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/* Validate parameters. */
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Assert(p_dmac);
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Assert(ul_num<=3);
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p_dmac->DMAC_CH_NUM[ul_num].DMAC_CTRLB = ul_ctrlB;
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}
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/**
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* \brief Set the DMAC configuration register of the specified DMA Channel.
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*
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* \param[out] p_dmac Module hardware register base address pointer
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* \param[in] ul_num DMA Channel number (range 0 to 3)
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* \param[in] ul_cfg Configuration of CFG register
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*/
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void dmac_channel_set_configuration(
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Dmac *p_dmac,
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uint32_t ul_num,
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uint32_t ul_cfg)
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{
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/* Validate parameters. */
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Assert(p_dmac);
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Assert(ul_num<=3);
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p_dmac->DMAC_CH_NUM[ul_num].DMAC_CFG = ul_cfg;
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}
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/**
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* \brief Initialize the DMA Channel for a single buffer transfer.
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*
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* \param[in,out] p_dmac Module hardware register base address pointer
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* \param[in] ul_num DMA Channel number (range 0 to 3)
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* \param[in] p_desc Pointer to a \ref dma_transfer_descriptor_t "transfer descriptor"
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*/
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void dmac_channel_single_buf_transfer_init(
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Dmac *p_dmac,
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uint32_t ul_num,
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dma_transfer_descriptor_t *p_desc)
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{
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/* Validate parameters. */
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Assert(p_dmac);
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Assert(ul_num<=3);
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Assert(p_desc);
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/* Clear any pending interrupts */
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p_dmac->DMAC_EBCISR;
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dmac_channel_set_source_addr(p_dmac, ul_num, p_desc->ul_source_addr);
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dmac_channel_set_destination_addr(p_dmac, ul_num,
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p_desc->ul_destination_addr);
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dmac_channel_set_descriptor_addr(p_dmac, ul_num, 0);
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dmac_channel_set_ctrlA(p_dmac, ul_num, p_desc->ul_ctrlA);
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dmac_channel_set_ctrlB(p_dmac, ul_num, p_desc->ul_ctrlB);
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}
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/**
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* \brief Initialize the DMA Channel for a multiple buffer transfer.
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*
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* \param[in,out] p_dmac Module hardware register base address pointer
|
|
* \param[in] ul_num DMA Channel number (range 0 to 3)
|
|
* \param[in] p_desc Pointer to a \ref dma_transfer_descriptor_t "transfer descriptor"
|
|
*/
|
|
void dmac_channel_multi_buf_transfer_init(
|
|
Dmac *p_dmac,
|
|
uint32_t ul_num,
|
|
dma_transfer_descriptor_t *p_desc)
|
|
{
|
|
/* Validate parameters. */
|
|
Assert(p_dmac);
|
|
Assert(ul_num<=3);
|
|
Assert(p_desc);
|
|
|
|
/* Clear any pending interrupts */
|
|
p_dmac->DMAC_EBCISR;
|
|
|
|
dmac_channel_set_descriptor_addr(p_dmac, ul_num, (uint32_t)p_desc);
|
|
dmac_channel_set_ctrlB(p_dmac, ul_num, 0);
|
|
}
|
|
|
|
/**
|
|
* \brief Stop a DMA transfer occurring on the specified DMA Channel.
|
|
*
|
|
* \note Under normal operation, the hardware disables a channel on transfer
|
|
* completion by clearing the DMAC_CHSR.ENAx register bit.
|
|
* The recommended way for software to disable a channel without losing data
|
|
* is to use the SUSPx bit in conjunction with the EMPTx bit in the Channel
|
|
* Handler Status Register.
|
|
*
|
|
* \param[in,out] p_dmac Module hardware register base address pointer
|
|
* \param[in] ul_num DMA Channel number (range 0 to 3)
|
|
*/
|
|
void dmac_channel_stop_transfer(
|
|
Dmac *p_dmac,
|
|
uint32_t ul_num)
|
|
{
|
|
uint32_t status;
|
|
|
|
/* Validate parameters. */
|
|
Assert(p_dmac);
|
|
Assert(ul_num<=3);
|
|
|
|
status = dmac_channel_get_status(p_dmac);
|
|
if (!(status & (DMAC_CHSR_ENA0 << ul_num))) {
|
|
/* The channel is already stopped. */
|
|
return;
|
|
} else {
|
|
/* Suspend channel and the channel FIFO receives no new data. */
|
|
dmac_channel_suspend(p_dmac, ul_num);
|
|
|
|
/* Check if the channel FIFO is empty. */
|
|
do {
|
|
status = dmac_channel_get_status(p_dmac);
|
|
if (status & (DMAC_CHSR_EMPT0 << ul_num)) {
|
|
break;
|
|
}
|
|
} while (1);
|
|
|
|
/* Disable the channel. */
|
|
dmac_channel_disable(p_dmac, ul_num);
|
|
/* Clear suspend flag. */
|
|
dmac_channel_resume(p_dmac, ul_num);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Check if the data transfer occurring on the specified DMA Channel is complete.
|
|
* \note This function is used in polling mode.
|
|
*
|
|
* \param[in] p_dmac Module hardware register base address pointer
|
|
* \param[in] ul_num DMA Channel number (range 0 to 3)
|
|
*
|
|
* \return The data transfer status.
|
|
* \retval 0 Data is transferring
|
|
* \retval 1 Data transfer complete
|
|
*/
|
|
uint32_t dmac_channel_is_transfer_done(
|
|
Dmac *p_dmac,
|
|
uint32_t ul_num)
|
|
{
|
|
uint32_t status;
|
|
|
|
/* Validate parameters. */
|
|
Assert(p_dmac);
|
|
Assert(ul_num<=3);
|
|
|
|
status = dmac_channel_get_status(p_dmac);
|
|
if (status & (DMAC_CHSR_ENA0 << ul_num)) {
|
|
return 0;
|
|
} else {
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief DMA Channel software single request.
|
|
*
|
|
* \param[in,out] p_dmac Module hardware register base address pointer
|
|
* \param[in] ul_num DMA Channel number (range 0 to 3)
|
|
* \param[in] ul_src_req Request a source transfer
|
|
* \param[in] ul_dst_req Request a destination transfer
|
|
*/
|
|
void dmac_soft_single_transfer_request(
|
|
Dmac *p_dmac,
|
|
uint32_t ul_num,
|
|
uint32_t ul_src_req,
|
|
uint32_t ul_dst_req)
|
|
{
|
|
uint32_t req;
|
|
|
|
/* Validate parameters. */
|
|
Assert(p_dmac);
|
|
Assert(ul_num<=3);
|
|
|
|
req = ul_src_req ? DMAC_SREQ_SSREQ0 : 0;
|
|
req |= ul_dst_req ? DMAC_SREQ_DSREQ0 : 0;
|
|
p_dmac->DMAC_SREQ |= (req << ul_num);
|
|
}
|
|
|
|
/**
|
|
* \brief DMA Channel software chunk request.
|
|
*
|
|
* \param[in,out] p_dmac Module hardware register base address pointer
|
|
* \param[in] ul_num DMA Channel number (range 0 to 3)
|
|
* \param[in] ul_src_req Request a source transfer
|
|
* \param[in] ul_dst_req Request a destination transfer
|
|
*/
|
|
void dmac_soft_chunk_transfer_request(
|
|
Dmac *p_dmac,
|
|
uint32_t ul_num,
|
|
uint32_t ul_src_req,
|
|
uint32_t ul_dst_req)
|
|
{
|
|
uint32_t req;
|
|
|
|
/* Validate parameters. */
|
|
Assert(p_dmac);
|
|
Assert(ul_num<=3);
|
|
|
|
req = ul_src_req ? DMAC_CREQ_SCREQ0 : 0;
|
|
req |= ul_dst_req ? DMAC_CREQ_DCREQ0 : 0;
|
|
p_dmac->DMAC_SREQ |= (req << ul_num);
|
|
}
|
|
|
|
/**
|
|
* \brief Set the DMA Channel's last transfer flag.
|
|
*
|
|
* \param[in,out] p_dmac Module hardware register base address pointer
|
|
* \param[in] ul_num Channel number
|
|
* \param[in] ul_src_flag Last source transfer flag
|
|
* \param[in] ul_dst_flag Last destination transfer flag
|
|
*/
|
|
void dmac_soft_set_last_transfer_flag(
|
|
Dmac *p_dmac,
|
|
uint32_t ul_num,
|
|
uint32_t ul_src_flag,
|
|
uint32_t ul_dst_flag)
|
|
{
|
|
uint32_t flag;
|
|
|
|
/* Validate parameters. */
|
|
Assert(p_dmac);
|
|
Assert(ul_num<=3);
|
|
|
|
flag = ul_src_flag ? DMAC_LAST_SLAST0 : 0;
|
|
flag |= ul_dst_flag ? DMAC_LAST_DLAST0 : 0;
|
|
p_dmac->DMAC_SREQ |= (flag << ul_num);
|
|
}
|
|
|
|
#if (SAM3XA || SAM4E) || defined(__DOXYGEN__)
|
|
|
|
#if !defined(__DOXYGEN__)
|
|
/** DMAC write protect key */
|
|
#define DMAC_WPKEY 0x50494Fu
|
|
#endif
|
|
|
|
/**
|
|
* \brief Enable/Disable the write protect of DMAC registers.
|
|
*
|
|
* \param[out] p_dmac Module hardware register base address pointer
|
|
* \param[in] ul_enable 1 to enable, 0 to disable
|
|
*/
|
|
void dmac_set_writeprotect(
|
|
Dmac *p_dmac,
|
|
uint32_t ul_enable)
|
|
{
|
|
/* Validate parameters. */
|
|
Assert(p_dmac);
|
|
|
|
if (ul_enable) {
|
|
p_dmac->DMAC_WPMR = DMAC_WPMR_WPKEY_PASSWD | DMAC_WPMR_WPEN;
|
|
} else {
|
|
p_dmac->DMAC_WPMR = DMAC_WPMR_WPKEY_PASSWD;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Get the DMAC register's write protect status.
|
|
*
|
|
* \param[in] p_dmac Module hardware register base address pointer
|
|
*
|
|
* \return Write protect status.
|
|
*/
|
|
uint32_t dmac_get_writeprotect_status(
|
|
Dmac *p_dmac)
|
|
{
|
|
/* Validate parameters. */
|
|
Assert(p_dmac);
|
|
|
|
return p_dmac->DMAC_WPSR;
|
|
}
|
|
#endif /* (SAM3XA || SAM4E) || defined(__DOXYGEN__) */
|