0c85453ace
Added the libraries to the repository Preliminary changes to fix slow startup when no network cable is connected
147 lines
5.2 KiB
C
147 lines
5.2 KiB
C
/**
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* \file
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*
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* \brief DMA Controller (DMAC) driver for SAM.
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*
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* Copyright (c) 2012 - 2013 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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#ifndef DMAC_H_INCLUDED
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#define DMAC_H_INCLUDED
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#include "compiler.h"
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/** @cond 0 */
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/**INDENT-OFF**/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**INDENT-ON**/
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/** @endcond */
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/**
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* \defgroup sam_driver_dmac_group DMA Controller (DMAC) Driver
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*
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* \par Purpose
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*
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* The DMA Controller (DMAC) is an AHB-central DMA controller core that
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* transfers data from a source peripheral to a destination peripheral
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* over one or more AMBA buses. This is a driver for configuration, enabling,
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* disabling and use of the DMAC peripheral.
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*
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* @{
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*/
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/** \brief DMAC priority mode */
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typedef enum {
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#if (SAM3U)
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DMAC_PRIORITY_FIXED = 0,
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DMAC_PRIORITY_ROUND_ROBIN = DMAC_GCFG_ARB_CFG
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#else
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DMAC_PRIORITY_FIXED = DMAC_GCFG_ARB_CFG_FIXED,
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DMAC_PRIORITY_ROUND_ROBIN = DMAC_GCFG_ARB_CFG_ROUND_ROBIN
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#endif
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} dmac_priority_mode_t;
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/** \brief DMA transfer descriptor, otherwise known as Linked List Item (LLI) */
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typedef struct {
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uint32_t ul_source_addr; /**< Source buffer address */
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uint32_t ul_destination_addr; /**< Destination buffer address */
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uint32_t ul_ctrlA; /**< Control A register settings */
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uint32_t ul_ctrlB; /**< Control B register settings */
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uint32_t ul_descriptor_addr; /**< Next descriptor address */
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} dma_transfer_descriptor_t;
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#define DMA_MAX_LENGTH 0xFFFu
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void dmac_init(Dmac *p_dmac);
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void dmac_set_priority_mode(Dmac *p_dmac, dmac_priority_mode_t mode);
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void dmac_enable(Dmac *p_dmac);
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void dmac_disable(Dmac *p_dmac);
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void dmac_enable_interrupt(Dmac *p_dmac, uint32_t ul_mask);
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void dmac_disable_interrupt(Dmac *p_dmac, uint32_t ul_mask);
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uint32_t dmac_get_interrupt_mask(Dmac *p_dmac);
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uint32_t dmac_get_status(Dmac *p_dmac);
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void dmac_channel_enable(Dmac *p_dmac, uint32_t ul_num);
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void dmac_channel_disable(Dmac *p_dmac, uint32_t ul_num);
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uint32_t dmac_channel_is_enable(Dmac *p_dmac, uint32_t ul_num);
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void dmac_channel_suspend(Dmac *p_dmac, uint32_t ul_num);
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void dmac_channel_resume(Dmac *p_dmac, uint32_t ul_num);
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void dmac_channel_keep(Dmac *p_dmac, uint32_t ul_num);
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uint32_t dmac_channel_get_status(Dmac *p_dmac);
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void dmac_channel_set_source_addr(Dmac *p_dmac,
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uint32_t ul_num, uint32_t ul_addr);
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void dmac_channel_set_destination_addr(Dmac *p_dmac,
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uint32_t ul_num, uint32_t ul_addr);
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void dmac_channel_set_descriptor_addr(Dmac *p_dmac,
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uint32_t ul_num, uint32_t ul_desc);
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void dmac_channel_set_ctrlA(Dmac *p_dmac, uint32_t ul_num, uint32_t ul_ctrlA);
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void dmac_channel_set_ctrlB(Dmac *p_dmac, uint32_t ul_num, uint32_t ul_ctrlB);
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void dmac_channel_set_configuration(Dmac *p_dmac, uint32_t ul_num,
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uint32_t ul_cfg);
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void dmac_channel_single_buf_transfer_init(Dmac *p_dmac,
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uint32_t ul_num, dma_transfer_descriptor_t *p_desc);
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void dmac_channel_multi_buf_transfer_init(Dmac *p_dmac,
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uint32_t ul_num, dma_transfer_descriptor_t *p_desc);
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void dmac_channel_stop_transfer(Dmac *p_dmac, uint32_t ul_num);
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uint32_t dmac_channel_is_transfer_done(Dmac *p_dmac, uint32_t ul_num);
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void dmac_soft_single_transfer_request(Dmac *p_dmac,
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uint32_t ul_num, uint32_t ul_src_req, uint32_t ul_dst_req);
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void dmac_soft_chunk_transfer_request(Dmac *p_dmac,
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uint32_t ul_num, uint32_t ul_src_req, uint32_t ul_dst_req);
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void dmac_soft_set_last_transfer_flag(Dmac *p_dmac,
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uint32_t ul_num, uint32_t ul_src_flag, uint32_t ul_dst_flag);
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#if (SAM3XA_SERIES || SAM4E)
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void dmac_set_writeprotect(Dmac *p_dmac, uint32_t ul_enable);
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uint32_t dmac_get_writeprotect_status(Dmac *p_dmac);
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#endif
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/** @} */
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/** @cond 0 */
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/**INDENT-OFF**/
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#ifdef __cplusplus
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}
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#endif
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/**INDENT-ON**/
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/** @endcond */
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#endif /* DMAC_H_INCLUDED */
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