efe13ef2f1
Added F (probing speed) and T (travel speed) parameters to M558 command Removed M210 command because home feed rates are defined in the homing files Increased UART interrupt priority to avoid dropping characters sent by PanelDue Bug fix: M558 P3 did not leave the Z probe control pin high Bug fix: in version 1.09j only, the move following a G92 E0 command was sometimes executed from an incorrect start point Fixed bugs with reads/writes from/to the SD card that spanned one or more whole sectors Updated to latest Atmel HSMCI driver
385 lines
13 KiB
C
385 lines
13 KiB
C
/**
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* \file
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*
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* \brief SAM4E DMA Controller (DMAC) driver.
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*
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* Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#ifndef DMAC_H_INCLUDED
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#define DMAC_H_INCLUDED
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/**
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* \defgroup asfdoc_sam_drivers_dmac_group SAM3A/3U/3X/4E DMA Controller (DMAC) Driver
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*
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* This driver for Atmel® | SMART ARM®-based microcontrollers
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* provides an interface for the configuration and management of the
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* device's Direct Memory Access DMA Controller (DMAC) functionality.
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*
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* The DMAC is an AHB-central DMA controller core that
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* transfers data from a source peripheral to a destination peripheral
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* over one or more AMBA buses. This is a driver for the configuration,
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* enabling, disabling, and use of the DMAC peripheral.
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*
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* Devices from the following series can use this module:
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* - Atmel | SMART SAM3A
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* - Atmel | SMART SAM3U
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* - Atmel | SMART SAM3X
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* - Atmel | SMART SAM4E
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*
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* The outline of this documentation is as follows:
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* - \ref asfdoc_sam_drivers_dmac_prerequisites
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* - \ref asfdoc_sam_drivers_dmac_module_overview
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* - \ref asfdoc_sam_drivers_dmac_special_considerations
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* - \ref asfdoc_sam_drivers_dmac_extra_info
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* - \ref asfdoc_sam_drivers_dmac_examples
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* - \ref asfdoc_sam_drivers_dmac_api_overview
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*
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*
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* \section asfdoc_sam_drivers_dmac_prerequisites Prerequisites
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*
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* There are no prerequisites for this module.
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*
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*
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* \section asfdoc_sam_drivers_dmac_module_overview Module Overview
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* The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers
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* data from a source peripheral to a destination peripheral over one or more AMBA
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* buses. One channel is required for each source/destination pair. In the
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* most basic configuration, the DMAC has one master interface and one channel. The
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* master interface reads the data from a source and writes it to a destination.
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* Two AMBA transfers are required for each DMAC data transfer. This is also known
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* as a dual-access transfer.
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*
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*
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* \section asfdoc_sam_drivers_dmac_special_considerations Special Considerations
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* There are no special considerations for this module.
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*
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*
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* \section asfdoc_sam_drivers_dmac_extra_info Extra Information
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*
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* For extra information, see \ref asfdoc_sam_drivers_dmac_extra. This includes:
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* - \ref asfdoc_sam_drivers_dmac_extra_acronyms
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* - \ref asfdoc_sam_drivers_dmac_extra_dependencies
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* - \ref asfdoc_sam_drivers_dmac_extra_errata
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* - \ref asfdoc_sam_drivers_dmac_extra_history
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*
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* \section asfdoc_sam_drivers_dmac_examples Examples
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*
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* For a list of examples related to this driver, see
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* \ref asfdoc_sam_drivers_dmac_exqsg.
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*
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*
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* \section asfdoc_sam_drivers_dmac_api_overview API Overview
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* @{
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*/
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#include <compiler.h>
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/** @cond */
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/**INDENT-OFF**/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**INDENT-ON**/
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/** @endcond */
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/** \brief DMAC priority mode */
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typedef enum {
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#if (SAM3U)
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/** Fixed priority arbiter */
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DMAC_PRIORITY_FIXED = 0,
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/** Modified round robin arbiter */
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DMAC_PRIORITY_ROUND_ROBIN = DMAC_GCFG_ARB_CFG
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#else
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/** Fixed priority arbiter */
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DMAC_PRIORITY_FIXED = DMAC_GCFG_ARB_CFG_FIXED,
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/** Modified round robin arbiter */
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DMAC_PRIORITY_ROUND_ROBIN = DMAC_GCFG_ARB_CFG_ROUND_ROBIN
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#endif
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} dmac_priority_mode_t;
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/** DMA transfer descriptor structure, otherwise known as a Linked List Item (LLI). */
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typedef struct {
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uint32_t ul_source_addr; /**< Source buffer address */
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uint32_t ul_destination_addr; /**< Destination buffer address */
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uint32_t ul_ctrlA; /**< Control A register settings */
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uint32_t ul_ctrlB; /**< Control B register settings */
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uint32_t ul_descriptor_addr; /**< Next descriptor address */
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} dma_transfer_descriptor_t;
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#if !defined(__DOXYGEN__)
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#define DMA_MAX_LENGTH 0xFFFu
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#endif /* !defined(__DOXYGEN__) */
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void dmac_init(Dmac *p_dmac);
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void dmac_set_priority_mode(Dmac *p_dmac, dmac_priority_mode_t mode);
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void dmac_enable(Dmac *p_dmac);
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void dmac_disable(Dmac *p_dmac);
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void dmac_enable_interrupt(Dmac *p_dmac, uint32_t ul_mask);
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void dmac_disable_interrupt(Dmac *p_dmac, uint32_t ul_mask);
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uint32_t dmac_get_interrupt_mask(Dmac *p_dmac);
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uint32_t dmac_get_status(Dmac *p_dmac);
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void dmac_channel_enable(Dmac *p_dmac, uint32_t ul_num);
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void dmac_channel_disable(Dmac *p_dmac, uint32_t ul_num);
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uint32_t dmac_channel_is_enable(Dmac *p_dmac, uint32_t ul_num);
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void dmac_channel_suspend(Dmac *p_dmac, uint32_t ul_num);
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void dmac_channel_resume(Dmac *p_dmac, uint32_t ul_num);
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void dmac_channel_keep(Dmac *p_dmac, uint32_t ul_num);
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uint32_t dmac_channel_get_status(Dmac *p_dmac);
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void dmac_channel_set_source_addr(Dmac *p_dmac,
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uint32_t ul_num, uint32_t ul_addr);
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void dmac_channel_set_destination_addr(Dmac *p_dmac,
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uint32_t ul_num, uint32_t ul_addr);
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void dmac_channel_set_descriptor_addr(Dmac *p_dmac,
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uint32_t ul_num, uint32_t ul_desc);
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void dmac_channel_set_ctrlA(Dmac *p_dmac, uint32_t ul_num, uint32_t ul_ctrlA);
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void dmac_channel_set_ctrlB(Dmac *p_dmac, uint32_t ul_num, uint32_t ul_ctrlB);
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void dmac_channel_set_configuration(Dmac *p_dmac, uint32_t ul_num,
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uint32_t ul_cfg);
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void dmac_channel_single_buf_transfer_init(Dmac *p_dmac,
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uint32_t ul_num, dma_transfer_descriptor_t *p_desc);
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void dmac_channel_multi_buf_transfer_init(Dmac *p_dmac,
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uint32_t ul_num, dma_transfer_descriptor_t *p_desc);
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void dmac_channel_stop_transfer(Dmac *p_dmac, uint32_t ul_num);
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uint32_t dmac_channel_is_transfer_done(Dmac *p_dmac, uint32_t ul_num);
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void dmac_soft_single_transfer_request(Dmac *p_dmac,
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uint32_t ul_num, uint32_t ul_src_req, uint32_t ul_dst_req);
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void dmac_soft_chunk_transfer_request(Dmac *p_dmac,
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uint32_t ul_num, uint32_t ul_src_req, uint32_t ul_dst_req);
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void dmac_soft_set_last_transfer_flag(Dmac *p_dmac,
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uint32_t ul_num, uint32_t ul_src_flag, uint32_t ul_dst_flag);
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#if (SAM3XA || SAM4E) || defined(__DOXYGEN__)
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void dmac_set_writeprotect(Dmac *p_dmac, uint32_t ul_enable);
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uint32_t dmac_get_writeprotect_status(Dmac *p_dmac);
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#endif
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/** @cond */
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/**INDENT-OFF**/
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#ifdef __cplusplus
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}
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#endif
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/**INDENT-ON**/
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/** @endcond */
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/** @} */
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/**
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* \page asfdoc_sam_drivers_dmac_extra Extra Information for Direct Memory Access Controller Driver
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*
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* \section asfdoc_sam_drivers_dmac_extra_acronyms Acronyms
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* Below is a table listing the acronyms used in this module, along with their
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* intended meanings.
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*
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* <table>
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* <tr>
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* <th>Acronym</th>
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* <th>Definition</th>
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* </tr>
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* <tr>
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* <td>AHB</td>
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* <td>AMBA High-performance Bus</td>
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* </tr>
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* <tr>
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* <td>AMBA</td>
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* <td>Advanced Microcontroller Bus Architecture</td>
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* </tr>
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* <tr>
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* <td>FIFO</td>
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* <td>First In First Out</td>
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* </tr>
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* <tr>
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* <td>LLI</td>
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* <td>Linked List Item</td>
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* </tr>
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* <tr>
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* <td>QSG</td>
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* <td>Quick Start Guide</td>
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* </tr>
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* </table>
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*
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*
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* \section asfdoc_sam_drivers_dmac_extra_dependencies Dependencies
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* This driver has the following dependencies:
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*
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* - None
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*
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*
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* \section asfdoc_sam_drivers_dmac_extra_errata Errata
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* There are no errata related to this driver.
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*
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*
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* \section asfdoc_sam_drivers_dmac_extra_history Module History
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* An overview of the module history is presented in the table below, with
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* details on the enhancements and fixes made to the module since its first
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* release. The current version of this corresponds to the newest version in
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* the table.
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*
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* <table>
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* <tr>
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* <th>Changelog</th>
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* </tr>
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* <tr>
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* <td>Initial document release</td>
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* </tr>
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* </table>
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*/
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/**
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* \page asfdoc_sam_drivers_dmac_exqsg Examples for Direct Memory Access Controller Driver
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*
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* This is a list of the available Quick Start Guides (QSGs) and example
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* applications for \ref asfdoc_sam_drivers_dmac_group. QSGs are simple examples with
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* step-by-step instructions to configure and use this driver in a selection of
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* use cases. Note that a QSG can be compiled as a standalone application or be
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* added to the user application.
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*
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* - \subpage asfdoc_sam_drivers_dmac_qsg
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* - \subpage asfdoc_sam_drivers_dmac_example
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*
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* \page asfdoc_sam_drivers_dmac_document_revision_history Document Revision History
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*
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* <table>
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* <tr>
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* <th>Doc. Rev.</td>
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* <th>Date</td>
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* <th>Comments</td>
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* </tr>
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* <tr>
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* <td>42291B</td>
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* <td>07/2015</td>
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* <td>Updated title of application note and added list of supported devices</td>
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* </tr>
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* <tr>
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* <td>42291A</td>
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* <td>05/2014</td>
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* <td>Initial document release</td>
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* </tr>
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* </table>
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*
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*/
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/**
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* \page asfdoc_sam_drivers_dmac_qsg Quick Start Guide for the DMAC driver
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*
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* This is the quick start guide for the \ref asfdoc_sam_drivers_dmac_group, with
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* step-by-step instructions on how to configure and use the driver for
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* a specific use case. The code examples can be
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* copied into the main application loop or any other function that will need
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* to control the DMAC module.
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*
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* \section asfdoc_sam_drivers_dmac_qsg_use_cases Use Cases
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* - \ref asfdoc_sam_drivers_dmac_qsg_basic
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*
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* \section asfdoc_sam_drivers_dmac_qsg_basic DMAC Basic Usage
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*
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* This use case will demonstrate how to initialize the DMAC module to
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* perform a single memory to memory transfer.
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*
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*
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* \section asfdoc_sam_drivers_dmac_qsg_basic_setup Setup Steps
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*
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* \subsection asfdoc_sam_drivers_dmac_qsg_basic_prereq Prerequisites
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*
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* This module requires the following service
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* - \ref clk_group "System Clock Management (sysclock)"
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*
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* \subsection asfdoc_sam_drivers_dmac_qsg_basic_setup_code Setup Code
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*
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* Add these macros and global variable to the top of your application's C-file:
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* \snippet dmac_example.c dmac_define_channel
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* \snippet dmac_example.c dmac_define_buffer
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*
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* Add this to the main loop or a setup function:
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* \snippet dmac_example.c dmac_init_clock
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*
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* \subsection asfdoc_sam_drivers_dmac_qsg_basic_setup_workflow Workflow
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*
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* -# Define the variables needed, in order to perform a data transfer:
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* \snippet dmac_example.c dmac_define_vars
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* -# Prepare the data buffer to be transferred:
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* \snippet dmac_example.c dmac_define_prepare_buffer
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* -# Initialize the DMAC module:
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* \snippet dmac_example.c dmac_init_module
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* -# Set the priority to round-robin:
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* \snippet dmac_example.c dmac_set_priority
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* -# Enable the DMAC module:
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* \snippet dmac_example.c dmac_enable_module
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* -# Configure the channel for:
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* - Enable stop on done
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* - Enable AHB protection
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* - Set the FIFO so that largest defined length AHB burst is performed
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* \snippet dmac_example.c dmac_configure_channel
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*
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* \section asfdoc_sam_drivers_dmac_qsg_basic_usage Usage Steps
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*
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* \subsection asfdoc_sam_drivers_dmac_qsg_basic_usage_code Usage Code
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* Configure the DMA source and destination buffer addresses:
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* \snippet dmac_example.c dmac_configure_for_single_transfer_1
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*
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* Configure DMA CTRLA:
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* - Set the buffer transfer size to DMA_BUF_SIZE
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* - Set the source transfer width to 32-bit
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* - Set the destination transfer width to 32-bit
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* \snippet dmac_example.c dmac_configure_for_single_transfer_2
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*
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* Configure DMA CTRLB:
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* - Disable source buffer descriptor fetch
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* - Disable destination buffer descriptor Fetch
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* - Enable memory-to-memory transfer
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* - Increment the source address
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* - Increment the destination address
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* \snippet dmac_example.c dmac_configure_for_single_transfer_3
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*
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* Initialize the DMA transfer:
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* \snippet dmac_example.c dmac_configure_for_single_transfer_4
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*
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* Start the DMA transfer:
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* \snippet dmac_example.c dmac_start_transfer
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*
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* Finally, poll for the DMA transfer to complete:
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* \snippet dmac_example.c dmac_wait_for_done
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*/
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#endif /* DMAC_H_INCLUDED */
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