Duet Ethernet now uses the PDC for SPI transfers
This commit is contained in:
David Crocker
parent
f4f6ad3c61
commit
01d439ddb4
3 changed files with 37 additions and 66 deletions
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@ -36,7 +36,7 @@ const Port TELNET_PORT = 23;
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const unsigned int TCP_MSS = 1460;
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const size_t NetworkTransactionCount = 8; // number of NetworkTransactions to be used for network IO
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const size_t NetworkBufferCount = 12; // number of 2K or 3K network buffers
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const size_t NetworkBufferCount = 16; // number of 2K or 3K network buffers
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// Define the following to use 3K buffers on the W5500 for the HTTP sockets and smaller buffers for everything else
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// It doesn't seem to work, the chip keeps telling us that 1 byte is available.
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@ -11,7 +11,7 @@
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// Define exactly one of the following as 1, the other as zero
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// The PDC seems to be too slow to work reliably without getting transmit underruns, so we use the DMAC now.
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#define USE_PDC 0 // use peripheral DMA controller
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#define USE_PDC 1 // use peripheral DMA controller
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#define USE_DMAC 0 // use general DMA controller
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#if USE_PDC
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@ -30,9 +30,11 @@ const unsigned int SpiPeripheralChannelId = 0; // we use NPCS0 as the slave se
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#if USE_PDC
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static Pdc *spi_pdc;
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static inline void spi_rx_dma_enable()
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{
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pdc_enable_transfer(spi_pdc, PERIPH_PTCR_RXTEN);
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pdc_enable_transfer(spi_pdc, PERIPH_PTCR_TXTEN); // we have to transmit in order to receive
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}
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static inline void spi_tx_dma_enable()
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@ -43,6 +45,7 @@ static inline void spi_tx_dma_enable()
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static inline void spi_rx_dma_disable()
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{
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pdc_disable_transfer(spi_pdc, PERIPH_PTCR_RXTDIS);
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pdc_disable_transfer(spi_pdc, PERIPH_PTCR_TXTDIS); // we have to transmit in order to receive
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}
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static inline void spi_tx_dma_disable()
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@ -52,23 +55,24 @@ static inline void spi_tx_dma_disable()
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static bool spi_dma_check_rx_complete()
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{
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return true;
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return pdc_read_rx_counter(spi_pdc) == 0;
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}
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static void spi_tx_dma_setup(const TransactionBuffer *buf, uint32_t maxTransmitLength)
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static void spi_tx_dma_setup(const uint8_t *buf, uint32_t length)
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{
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pdc_packet_t pdc_spi_packet;
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pdc_spi_packet.ul_addr = reinterpret_cast<uint32_t>(buf);
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pdc_spi_packet.ul_size = buf->PacketLength() * 4; // need length in bytes
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pdc_spi_packet.ul_size = length;
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pdc_tx_init(spi_pdc, &pdc_spi_packet, NULL);
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}
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static void spi_rx_dma_setup(const TransactionBuffer *buf)
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static void spi_rx_dma_setup(uint8_t *buf, uint32_t length)
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{
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pdc_packet_t pdc_spi_packet;
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pdc_spi_packet.ul_addr = reinterpret_cast<uint32_t>(buf);
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pdc_spi_packet.ul_size = TransactionBuffer::MaxReceiveBytes;
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pdc_spi_packet.ul_size = length;
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pdc_rx_init(spi_pdc, &pdc_spi_packet, NULL);
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pdc_tx_init(spi_pdc, &pdc_spi_packet, NULL); // we have to transmit in order to receive
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}
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#endif
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@ -152,51 +156,6 @@ static void spi_dma_disable()
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spi_rx_dma_disable();
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}
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#if 0
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/**
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* \brief Set SPI slave transfer.
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*/
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static void spi_slave_dma_setup(bool dataToSend, bool allowReceive)
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{
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#if USE_PDC
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pdc_disable_transfer(spi_pdc, PERIPH_PTCR_TXTDIS | PERIPH_PTCR_RXTDIS);
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TransactionBuffer *outBufPointer = (dataToSend) ? &outBuffer : reinterpret_cast<TransactionBuffer*>(&dummyOutBuffer);
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spi_tx_dma_setup(outBufPointer);
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if (allowReceive)
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{
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outBufPointer->SetDataTaken();
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spi_rx_dma_setup(&inBuffer);
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pdc_enable_transfer(spi_pdc, PERIPH_PTCR_TXTEN | PERIPH_PTCR_RXTEN);
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}
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else
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{
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outBufPointer->ClearDataTaken();
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pdc_enable_transfer(spi_pdc, PERIPH_PTCR_TXTEN);
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}
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#endif
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#if USE_DMAC
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spi_dma_disable();
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TransactionBuffer *outBufPointer = (dataToSend) ? &outBuffer : reinterpret_cast<TransactionBuffer*>(&dummyOutBuffer);
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if (allowReceive)
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{
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spi_rx_dma_setup(&inBuffer);
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spi_rx_dma_enable();
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// outBufPointer->SetDataTaken();
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}
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else
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{
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// outBufPointer->ClearDataTaken();
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}
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// spi_tx_dma_setup(outBufPointer, (dataToSend) ? TransactionBuffer::MaxTransferBytes : 4 * TransactionBuffer::headerDwords);
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spi_tx_dma_enable();
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#endif
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}
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#endif
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#endif
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namespace WizSpi
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@ -204,16 +163,16 @@ namespace WizSpi
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// Initialise the SPI interface
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void Init()
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{
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#if USE_PDC
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#if USE_PDC
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spi_pdc = spi_get_pdc_base(SPI);
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// The PDCs are masters 2 and 3 and the SRAM is slave 0. Give the PDCs the highest priority.
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// The PDCs are masters 2 and 3 and the SRAM is slave 0. Give the receive PDCs the highest priority.
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matrix_set_master_burst_type(0, MATRIX_ULBT_8_BEAT_BURST);
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matrix_set_slave_default_master_type(0, MATRIX_DEFMSTR_LAST_DEFAULT_MASTER);
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matrix_set_slave_priority(0, (3 << MATRIX_PRAS0_M2PR_Pos) | (3 << MATRIX_PRAS0_M3PR_Pos));
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matrix_set_slave_slot_cycle(0, 8);
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#endif
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#endif
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#if USE_DMAC
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#if USE_DMAC
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pmc_enable_periph_clk(ID_DMAC);
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dmac_init(DMAC);
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dmac_set_priority_mode(DMAC, DMAC_PRIORITY_ROUND_ROBIN);
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@ -225,7 +184,7 @@ namespace WizSpi
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// If we leave it at the default value of 511 clock cycles, we get transmit underruns due to the HSMCI using the bus for too long.
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// A value of 8 seems to work. I haven't tried other values yet.
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matrix_set_slave_slot_cycle(0, 8);
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#endif
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#endif
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// Set up the SPI pins
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ConfigurePin(g_APinDescription[APIN_SPI_SCK]);
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@ -402,6 +361,17 @@ namespace WizSpi
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(void)SPI->SPI_RDR; // clear previous data
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}
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#if USE_PDC
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spi_rx_dma_setup(rx_data, len);
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spi_rx_dma_enable();
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while (pdc_read_tx_counter(spi_pdc) != 0) { }
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uint32_t timeout = SPI_TIMEOUT;
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while (!spi_dma_check_rx_complete() && timeout != 0)
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{
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--timeout;
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}
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spi_rx_dma_disable();
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#else
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const uint32_t dOut = 0x000000FF;
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SPI->SPI_TDR = dOut; // send first byte
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while (--len != 0)
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@ -428,6 +398,7 @@ namespace WizSpi
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}
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*rx_data++ = (uint8_t)SPI->SPI_RDR; // Get last byte from receive register
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#endif
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}
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return SPI_OK;
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}
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@ -435,24 +406,24 @@ namespace WizSpi
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// Send some data
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spi_status_t SendBurst(const uint8_t* tx_data, size_t len)
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{
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#if USE_PDC
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spi_tx_dma_setup(tx_data, len);
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spi_tx_dma_enable();
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while (pdc_read_tx_counter(spi_pdc) != 0) { }
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spi_tx_dma_disable();
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#else
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for (uint32_t i = 0; i < len; ++i)
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{
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uint32_t dOut = (uint32_t)*tx_data++;
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if (i + 1 == len)
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{
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dOut |= SPI_TDR_LASTXFER;
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}
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if (waitForTxReady())
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{
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return SPI_ERROR_TIMEOUT;
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}
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// Write to transmit register
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SPI->SPI_TDR = dOut;
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SPI->SPI_TDR = dOut; // write to transmit register
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(void)SPI->SPI_RDR;
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}
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#endif
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return SPI_OK;
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}
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@ -14,7 +14,7 @@
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#include "Libraries/Math/Matrix.h"
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#ifdef DUET_NG
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const unsigned int DdaRingLength = 40;
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const unsigned int DdaRingLength = 30;
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#else
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// We are more memory-constrained on the SAM3X
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const unsigned int DdaRingLength = 20;
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