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Packing of the PCB

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This commit is contained in:
Thomas Schwery 2018-07-20 18:27:50 +02:00
parent 4038a0b9c0
commit 857bd2ac08
2 changed files with 1318 additions and 1333 deletions
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2573
tests_pcb/sample_stm32/keyboard_pcb.kicad_pcb
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78
tests_pcb/sample_stm32/keyboard_pcb.pro
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@ -1,29 +1,10 @@
update=22/05/2015 07:44:53 update=Fri 20 Jul 2018 17:41:35 CEST
version=1 version=1
last_client=kicad last_client=kicad
[general] [general]
version=1 version=1
RootSch= RootSch=
BoardNm= BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb] [cvpcb]
version=1 version=1
NetIExt=net NetIExt=net
@ -31,3 +12,60 @@ NetIExt=net
version=1 version=1
LibDir= LibDir=
[eeschema/libraries] [eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.1524
MinViaDiameter=0.6858
MinViaDrill=0.3302
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.1524
ViaDiameter1=0.6858
ViaDrill1=0.3302
dPairWidth1=0.1524
dPairGap1=0.1524
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgesAndCourtyardsLineWidth=0.15
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.2
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Netclasses]
[pcbnew/Netclasses/1]
Name=Power
Clearance=0.1524
TrackWidth=0.3048
ViaDiameter=0.6858
ViaDrill=0.3302
uViaDiameter=0.6858
uViaDrill=0.3302
dPairWidth=0.1524
dPairGap=0.1524
dPairViaGap=0.25